MT8VDDT6464AY-335F3 Micron Technology Inc, MT8VDDT6464AY-335F3 Datasheet - Page 15
![no-image](/images/manufacturer_photos/0/4/441/micron_technology_inc_sml.jpg)
MT8VDDT6464AY-335F3
Manufacturer Part Number
MT8VDDT6464AY-335F3
Description
MODULE DDR SDRAM 512MB 184-DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT8VDDT3264AG-335G6.pdf
(30 pages)
Specifications of MT8VDDT6464AY-335F3
Memory Type
DDR SDRAM
Memory Size
512MB
Speed
333MT/s
Package / Case
184-DIMM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 13: I
DDR SDRAM components only
Notes: 1–5, 8, 10, 12, 48; notes appear on pages 19–22; 0°C ≤ T
pdf: 09005aef80867ab3, source: 09005aef80867a99
DD8C16_32_64x64AG.fm - Rev. G 9/04 EN
OPERATING CURRENT: One device bank; Active-Precharge;
(MIN);
clock cycle; Address and control inputs changing once every two clock
cycles
OPERATING CURRENT: One device bank; Active-Read-Pre-charge;
Burst = 4;
control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks
idle; Power-down mode;
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;
t
changing once per clock cycle. V
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active;
Power-down mode;
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank;
Active-Precharge;
inputs changing twice per clock cycle; Address and other control inputs
changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device
bank active; Address and control inputs changing once per clock
cycle;
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device
bank active; Address and control inputs changing once per clock
cycle;
clock cycle
AUTO REFRESH CURRENT
SELF REFRESH CURRENT: CKE ≤ 0.2V
OPERATING CURRENT: Four device bank interleaving READs
(BL= 4) with auto precharge,
(MIN); Address and control inputs change only during Active, READ,
or WRITE commands
CK =
t
t
t
CK (MIN); CKE = HIGH; Address and other control inputs
CK =
CK =
t
CK =
t
RC =
t
t
CK (MIN); I
CK (MIN); DQ, DM, and DQS inputs changing twice per
t
CK (MIN); DQ, DM, and DQS inputs changing once per
t
DD
RC (MIN);
t
RC =
t
Specifications and Conditions – 256MB
CK =
PARAMETER/CONDITION
t
OUT
RAS (MAX);
t
CK =
t
t
CK (MIN); CKE = LOW
CK =
= 0mA
t
RC = minimum
t
CK (MIN); CKE = LOW
IN
t
CK (MIN); I
= V
t
CK =
REF
t
CK (MIN); DQ, DM, and DQS
for DQ, DQS, and DM
OUT
t
RC allowed;
= 0mA; Address and
t
t
REFC =
REFC = 7.8125µs
t
t
RFC (MIN)
CK =
t
RC =
15
A
≤ +70°C; V
t
CK
t
128MB, 256MB, 512MB (x64, SR)
RC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM UDIMM
I
I
I
SYM
I
I
I
I
DD 4 W
I
I
DD 3 N
DD 4 R
I
DD 5 A
I
I
DD 2 P
DD 2 F
DD 3 P
DD 0
DD 1
DD 5
DD 6
DD 7
DD
= V
DD
1,000
1,360
1,400
1,400
2,040
3,280
-335
400
240
480
32
48
32
Q = +2.5V ±0.2V
MAX
1,000
1,280
1,200
1,200
1,880
2,800
-262
360
200
400
32
48
32
-26A/
1,160
1,200
1,200
1,880
2,800
-265
960
360
200
400
32
48
32
UNITS
©2004 Micron Technology. Inc.
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
NOTES
21, 28,
21, 28,
20, 42
20, 42
20, 41
20, 42
20, 44
24, 44
20, 43
44
45
44
20
9