MT18VDVF12872G-40BF4 Micron Technology Inc, MT18VDVF12872G-40BF4 Datasheet

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MT18VDVF12872G-40BF4

Manufacturer Part Number
MT18VDVF12872G-40BF4
Description
MODULE DDR 1GB 184-DIMM VLP
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT18VDVF12872G-40BF4

Memory Type
DDR SDRAM
Memory Size
1GB
Speed
400MT/s
Package / Case
184-DIMM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
DDR SDRAM VLP RDIMM
MT18VDVF12872 – 1GB
For component data sheets, refer to Micron’s Web site:
Features
• 184-pin, very low profile registered dual in-line
• Fast data transfer rates: PC2700 or PC3200
• 1GB (128 Meg x 72)
• Supports ECC error detection and correction
• V
• V
• 2.5V I/O (SSTL_2-compatible)
• Internal pipelined double data rate (DDR)
• Bidirectional data strobe (DQS) transmitted/
• Differential clock inputs (CK and CK#)
• Multiple internal device banks for concurrent
• Single rank
• Selectable burst lengths (BL): 2, 4, or 8
• Auto precharge option
• Auto refresh and self refresh modes: 7.8125µs
• Serial presence-detect (SPD) with EEPROM
• Selectable CAS latency (CL) for maximum
• Gold edge contacts
Table 1:
PDF: 09005aef81c7380b/Source: 09005aef81c7380e
DVF18C_128x72.fm - Rev. C 11/07 EN
memory module (VLP RDIMM)
(-40B: V
2n-prefetch architecture
received with data—that is, source-synchronous
data capture
operation
maximum average periodic refresh interval
compatibility
DD
DDSPD
Speed
Grade
-40B
-335
= V
DD
DD
= +2.3V to +3.6V
Q = +2.5V
= V
Key Timing Parameters
Products and specifications discussed herein are subject to change by Micron without notice.
Nomenclature
DD
Notes:
Industry
Q = +2.6V)
PC3200
PC2700
1. The values of
actual DDR SDRAM device specifications are 15ns.
CL = 3
400
t
Data Rate (MT/s)
RCD and
CL = 2.5
333
333
t
www.micron.com
RP for -335 modules show 18ns to align with industry specifications;
1
1GB (x72, ECC, SR): 184-Pin DDR VLP RDIMM
Figure 1:
Notes: 1. Contact Micron for industrial temperature
Options
• Operating temperature
• Package
• Memory clock, speed, CAS latency
CL = 2
PCB height: 18.29mm (0.72in)
266
266
– Commercial (0°C ≤ T
– Industrial (–40°C ≤ T
– 184-pin DIMM (standard)
– 184-pin DIMM (Pb-free)
– 5.0ns (200 MHz), 400 MT/s, CL = 3
– 6.0ns (166 MHz), 333 MT/s, CL = 2.5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2. CL = CAS (READ) latency; registered mode
module offerings.
adds one clock cycle to CL.
184-Pin VLP RDIMM (MO-206)
t
(ns)
RCD
15
18
A
A
1
(ns)
≤ +85°C)
≤ +70°C)
t
15
18
RP
©2005 Micron Technology, Inc. All rights reserved.
2
(ns)
t
55
60
RC
Marking
Features
None
-40B
-335
Notes
G
Y
I
1

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MT18VDVF12872G-40BF4 Summary of contents

Page 1

... 400 333 266 – 333 266 t t RCD and RP for -335 modules show 18ns to align with industry specifications; Micron Technology, Inc., reserves the right to change products or specifications without notice. 1 184-Pin VLP RDIMM (MO-206) 1 ≤ +70°C) A ≤ +85° module offerings. adds one clock cycle to CL. ...

Page 2

... Part Number Density MT18VDVF12872G-40B__ MT18VDVF12872Y-40B__ MT18VDVF12872G-335__ MT18VDVF12872Y-335__ Notes: 1. Data sheets for the base device can be found on Micron’s Web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT18VDVF12872Y-335F1. ...

Page 3

Pin Assignments and Descriptions Table 4: Pin Assignments 184-Pin VLP RDIMM Front Pin Symbol Pin Symbol Pin Symbol Pin Symbol DQ17 47 REF 2 DQ0 25 DQS2 DQ1 ...

Page 4

Table 5: Pin Descriptions Symbol A0–A12 BA0, BA1 CK0, CK0# CKE0 RAS#, CAS#, WE# RESET# S0# SA0–SA2 SCL CB0–CB7 DQ0–DQ63 DQS0–DQS17 SDA DDSPD V REF PDF: 09005aef81c7380b/Source: 09005aef81c7380e DVF18C_128x72.fm - Rev. ...

Page 5

Functional Block Diagram Figure 2: Functional Block Diagram V SS RS0# U6, U17 R RAS# RRAS#: DDR SDRAM e CAS# RCAS#: DDR SDRAM g CKE0 RCKE0: DDR SDRAM i WE# s RWE#: DDR SDRAM t A0–A12 RA0–RA12: DDR SDRAM e ...

Page 6

... This module uses a DDR SDRAM device with four internal banks. DDR SDRAM modules use a double data rate architecture to achieve high-speed opera- tion. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single ...

Page 7

... Simulations are significantly more accurate and realistic than a gross estimation of module capacitance when inductance and delay parameters associated with trace lengths are used in simulations. JEDEC modules are currently designed using simulations to close timing budgets. Component AC Timing and Operating Conditions Recommended AC operating conditions are given in the DDR component data sheets. Component specifications are available on Micron’ ...

Page 8

I Specifications DD Table 8: I Specifications and Conditions – 1GB DD Values are shown for the MT46V128M4 DDR SDRAM only and are computed from values specified in the 512Mb (128 Meg x 4) component data sheet Parameter/Condition Operating one ...

Page 9

Register and PLL Specifications Table 9: Register Specifications SSTV16859 devices or equivalent JESD82-4B Parameter Symbol DC high-level input voltage DC low-level input voltage AC high-level ...

Page 10

Table 10: PLL Specifications CVF857 device or equivalent JESD82-1A Parameter DC high-level input voltage DC low-level input voltage Input voltage (limits) Input differential-pair cross voltage Input differential voltage Input differential voltage Input current Dynamic supply current Dynamic supply current Dynamic ...

Page 11

Serial Presence-Detect Table 12: Serial Presence-Detect EEPROM DC Operating Conditions Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage 3mA OUT Input leakage current GND ...

Page 12

Module Dimensions Figure 3: 184-Pin DDR VLP RDIMM 2.0 (0.079) R (4X 2.5 (0.098) D (2X) 2.31 (0.091) TYP Pin 1 2.21 (0.087) TYP 1.27 (0.05) 1.0 (0.039) TYP U12 U13 Pin 184 Notes: 1. All dimensions are ...

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