MT18VDDT12872AG-40BF1 Micron Technology Inc, MT18VDDT12872AG-40BF1 Datasheet
MT18VDDT12872AG-40BF1
Specifications of MT18VDDT12872AG-40BF1
Related parts for MT18VDDT12872AG-40BF1
MT18VDDT12872AG-40BF1 Summary of contents
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... ECC, DR), PC3200 184-PIN DDR SDRAM UDIMM MT18VDDT3272A – 256MB MT18VDDT6472A – 512MB MT18VDDT12872A – 1GB For the latest data sheet, please refer to the Micron site: www.micron.com/products/modules Figure 1: 184-Pin DIMM (MO-206) 1.25in. (31.75mm) OPTIONS • Package 184-pin DIMM (Standard) 184-pin DIMM (Lead-free) • ...
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... Part Numbers and Timing Parameters PART NUMBER MT18VDDT3272AG-40B__ MT18VDDT3272AY-40B__ MT18VDDT6472AG-40B__ MT18VDDT6472AY-40B__ MT18VDDT12872AG-40B__ MT18VDDT12872AY-40B__ NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT18VDDT6472AG-40BB1. pdf: 09005aef80814e61, source: 09005aef80a43eed DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN ...
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Table 3: Pin Assignment (184-Pin DIMM Front PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL DQ17 47 REF 2 DQ0 25 DQS2 DQ1 DQS0 ...
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Table 5: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information PIN NUMBERS 63, 65, 154 WE#, CAS#, RAS# 16, 17, 75, 76, 137, 138 CK0, CK0#, CK1, CK1#, ...
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Table 5: Pin Descriptions (Continued) Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information PIN NUMBERS 12, 13, 19, 20, 23, DQ0–DQ63 24, 28, 31, 33, 35, ...
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... WE# CKE0 CKE1 NOTE: 1. All resistor values are 22 unless otherwise specified. 2. Per industry standard, Micron modules utilize various component speed grades, as referenced in the module part number guide at www.micron.com/numberguide. pdf: 09005aef80814e61, source: 09005aef80a43eed DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN 256MB, 512MB, 1GB (x72, ECC, DR), PC3200 ...
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... DDR SDRAM modules use internally configured quad-bank DDR SDRAM devices. DDR SDRAM modules use a double data rate archi- tecture to achieve high-speed operation. Double data rate architecture is essentially a 2n-prefetch architec- ture with an interface designed to transfer two data words per clock cycle at the I/O pins ...
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... BA0 A11 A10 Operating Mode * M13 and M12 (BA1and BA0) must be “0, 0” to select the base mode register (vs. the extended mode register). 512MB, 1GB Modules BA1 BA0 A12 A11 A10 Operating Mode * M14 and M13 (BA1 and BA0) must be “0, 0” to select the base mode register (vs ...
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Table 6: Burst Definition Table STARTING BURST COLUMN ORDER OF ACCESSES WITHIN LENGTH ADDRESS TYPE = SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1 ...
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... DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN 256MB, 512MB, 1GB (x72, ECC, DR), PC3200 184-PIN DDR SDRAM UDIMM Figure 6: Extended Mode Register Definition Diagram 256MB Module BA1 BA0 A11 A10 512MB, 1GB Modules BA1 BA0 A12 A11 A10 E12 E11 E10 ...
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Commands Table 8, Commands Truth Table, and Table 9, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH; ...
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Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...
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Table 12: I Specifications and Conditions – 256MB DD DDR SDRAM components only Notes: 1–5, 8, 10, 12; notes appear on pages 19–21; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN); CK ...
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Table 13: I Specifications and Conditions – 512MB DD DDR SDRAM components only Notes: 1–5, 8, 10, 12; notes appear on pages 19–21; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN); CK ...
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Table 14: I Specifications and Conditions – 1GB DD DDR SDRAM components only Notes: 1–5, 8, 10, 12; notes appear on pages 19–21; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN); CK ...
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Table 15: Capacitance Note: 11; notes appear on pages 19–21 PARAMETER Input/Output Capacitance: DQ, DQS, DM Input Capacitance: Command and Address Input Capacitance: S#, CKE Input Capacitance: CK, CK# pdf: 09005aef80814e61, source: 09005aef80a43eed DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN 256MB, ...
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Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions Notes: 1–5, 8, 12–15, 29, 31; notes appear on pages 19–21; 0°C AC CHARACTERISTICS PARAMETER Access window of DQs from CK/CK# CK high-level width CK low-level width Clock ...
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Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes: 1–5, 8, 12–15, 29, 31; notes appear on pages 19–21; 0°C AC CHARACTERISTICS PARAMETER ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS ...
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Notes 1. All voltages referenced Tests for AC timing and electrical AC and DC DD characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are ...
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The valid data window is derived by achieving t t other specifications CK/2 QHS). The data valid window derates in ...
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The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10 percent, for device drain-to-source volt- ages from 0.1V to 1.0 Volt. 34. The voltage levels used are derived from a mini- mum ...
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Initialization To ensure device operation the DRAM must be ini- tialized as described below: 1. Simultaneously apply power Apply V and then V power. REF TT 3. Assert and hold CKE at a LVCMOS logic low. 4. ...
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... The component case temperature measurements shown above were obtained experimentally. The typical system to be used for experimental purposes is a dual-processor 600 MHz work station, fully loaded, with four comparable registered memory modules. Case temperatures charted represent worst-case component locations on modules installed in the internal slots of the system. ...
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SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 11, Data Validity, and Figure ...
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Table 17: EEPROM Device Select Code Most significant bit (b7) is sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 18: EEPROM Operating Modes MODE RW BIT Current Address Read Random Address Read Sequential ...
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Table 19: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA ...
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Table 21: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” BYTE DESCRIPTION 0 Number of SPD Bytes Used by Micron 1 Total Number of Bytes in SPD Device 2 Fundamental Memory Type 3 Number of Row Addresses ...
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Table 21: Serial Presence-Detect Matrix (Continued) “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” BYTE DESCRIPTION 31 Module Rank Density 32 Address And Command Setup Time Address And Command Hold Time Data/ Data Mask ...
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Figure 15: 184-PIN DIMM Dimensions 0.079 (2.00) R (4X 0.098 (2.50) D (2X) 0.091 (2.30) TYP. PIN 1 0.091 (2.30) 0.050 (1.27) TYP. U19 U10 U11 PIN 184 1.95 (49.53) NOTE: All dimensions in inches (millimeters); Data Sheet ...