MT9HTF12872KY-53EA1 Micron Technology Inc, MT9HTF12872KY-53EA1 Datasheet - Page 11

• Manufacturer Part Number: MT9HTF12872KY-53EA1
• Description: MODULE DDR2 1GB 244-MDIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9HTF12872KY-53EA1

• Memory Type: DDR2 SDRAM
• Memory Size: 1GB
• Speed: 533MT/s
• Package / Case: 244-MDIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 11:
PDF: 09005aef817ab1fc/Source: 09005aef817ab1dd
HTF9C32_64_128x72K.fm - Rev. C 9/06 EN
Parameter/Condition
Operating one bank active-precharge current;
t
commands; Address bus inputs are switching; Data bus inputs are
switching
Operating one bank active-read-precharge current; I
= 4, CL = CL (I
(I
commands; Address bus inputs are switching; Data pattern is same as
I
Precharge power-down current; All device banks idle;
CKE is LOW; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge quiet standby current; All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current; All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching;
Data bus inputs are switching
Active power-down current; All device banks open;
=
inputs are stable; Data bus inputs are floating
Active standby current; All device banks open;
t
commands; Other control and address bus inputs are switching; Data bus
inputs are switching
Operating burst write current; All device banks open, continuous
burst writes; BL = 4, CL = CL (I
MAX (I
commands; Address bus inputs are switching; Data bus inputs are
switching
Operating burst read current; All device banks open, continuous burst
reads, I
t
commands; Address bus inputs are switching; Data bus inputs are
switching
Burst refresh current;
(I
control and address bus inputs are switching; Data bus inputs are
switching
Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current; All device banks
interleaving reads, I
t
(I
inputs are stable during deselects; Data bus inputs are switching; See
I
RC (I
DD
RAS MAX (I
RAS MAX (I
CK (I
DD
DD
DD
DD
t
CK (I
4W
7 Conditions for detail
),
) interval; CKE is HIGH, S# is HIGH between valid commands; Other
); CKE is HIGH, S# is HIGH between valid commands; Address bus
DD
DD
t
RCD =
DD
DD
OUT
),
);
),
t
); CKE is LOW; Other control and address bus
t
RAS =
CK =
t
= 0mA; BL = 4, CL = CL (I
RP =
DD
DD
t
DD
RCD (I
I
Values shown for DDR2 SDRAM components only
),
),
DD
t
), AL = 0;
CK (I
t
t
t
t
RP =
RP =
RAS MIN (I
RP (I
Specifications and Conditions – 1GB
DD
OUT
DD
DD
t
t
); CKE is HIGH, S# is HIGH between valid
RP (I
RP (I
),
= 0mA; BL = 4, CL = CL (I
t
); CKE is HIGH, S# is HIGH between valid
CK =
t
t
CK =
RC =
DD
DD
DD
DD
); CKE is HIGH, S# is HIGH between valid
); CKE is HIGH, S# is HIGH between valid
256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 Registered MiniDIMM
t
); CKE is HIGH, S# is HIGH between valid
CK (I
t
t
CK (I
RC (I
), AL = 0;
DD
DD
DD
DD
), AL = 0;
); REFRESH command at every
),
),
t
t
t
RC =
RRD =
CK =
t
RC (I
t
t
CK (I
CK =
DD
t
RRD (I
t
CK =
), AL =
t
t
DD
CK =
CK =
DD
t
CK (I
),
t
DD
),
CK
t
t
CK (I
RAS =
t
t
),
t
t
OUT
RAS =
t
CK (I
t
CK (I
CK =
RCD (I
CK =
DD
t
Fast PDN Exit
MR[12] = 0
Slow PDN Exit
MR[12] = 1
RCD =
11
DD
),
= 0mA; BL
DD
DD
t
t
t
),
t
RAS =
RAS MIN
CK (I
t
CK (I
DD
RAS
); CKE is
),
t
RAS =
t
) - 1 ×
t
RCD
RC =
t
DD
DD
RFC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
);
);
Symbol -80E/-
I
I
I
I
I
I
I
DD
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
2Q
2N
3N
2P
3P
4R
0
1
5
6
7
1,440
1,440
2,115
3,015
800
810
990
450
450
360
540
63
90
63
Electrical Specifications
1,215
1,215
1,935
2,520
-667
765
900
360
360
270
495
63
90
63
©2005 Micron Technology, Inc. All rights reserved.
1,125
1,125
1,890
2,430
-53E
630
855
360
360
270
405
63
90
63
1,845
2,340
-40E
630
810
315
315
270
360
945
945
63
90
63
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA