MT8VDDT6464HDG-335F2 Micron Technology Inc, MT8VDDT6464HDG-335F2 Datasheet - Page 4

• Manufacturer Part Number: MT8VDDT6464HDG-335F2
• Description: MODULE DDR 512MB 200-SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8VDDT6464HDG-335F2

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 333MT/s
• Package / Case: 200-SODIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 200SODIMM
• Device Core Size: 64b
• Organization: 64Mx64
• Total Density: 512MByte
• Chip Density: 512Mb
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 800mA
• Number Of Elements: 8
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 6:
PDF: 09005aef80765fab/Source: 09005aef806e1d28
DD8C32_64x64HD.fm - Rev. E 11/08 EN
RAS#, CAS#, WE#
DQS0–DQS7
CKE0, CKE1
DQ0–DQ63
CK0, CK0#,
DM0–DM7
CK1, CK1#
BA0, BA1
SA0–SA2
Symbol
S0#, S1#
A0–A12
V
Pin Descriptions
SDA
DDSPD
V
V
SCL
V
NC
REF
DD
SS
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
–
Description
Address inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE commands, to
select one location out of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether the PRECHARGE
applies to one device bank (A10 LOW, device bank selected by BA0 and BA1)
or all device banks (A10 HIGH). The address inputs also provide the op-code
during a MODE REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded during the LOAD
MODE REGISTER command.
Bank address: BA0 and BA1 define the device bank to which an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied.
Clock: CK and CK# are differential clock inputs. All control, command, and
address input signals are sampled on the crossing of the positive edge of CK
and the negative edge of CK#. Output data (DQ and DQS) is referenced to the
crossings of CK and CK#.
Clock enable: CKE enables (registered HIGH) and CKE disables (registered
LOW) the internal clock, input buffers, and output drivers.
Input data mask: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH, along with that input data, during a write
access. DM is sampled on both edges of DQS. Although DM pins are input-only,
the DM loading is designed to match that of DQ and DQS pins.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command
being entered.
Chip selects: S# enables (registered LOW) and disables (registered HIGH) the
command decoder.
Presence-detect address inputs: These pins are used to configure the SPD
EEPROM address range on the I
Serial clock for SPD EEPROM: SCL is used to synchronize the presence-detect
data transfer to and from the module.
Data input/output: Data bus.
Data strobe: Output with read
write data. Center-aligned with write data. Used to capture data.
Serial data: SDA is a bidirectional pin used to transfer addresses and data into
and out of the presence-detect portion of the module.
Power supply: +2.5V ±0.2V (-40B: +2.6V ±0.1V).
Serial EEPROM power supply: +2.3V to +3.6V.
SSTL_2 reference voltage (V
Ground.
No connect: These pins are not connected on the module.
256MB, 512MB (x64, DR): 200-Pin DDR SDRAM SODIMM
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
/2).
Pin Assignments and Descriptions
2
data.
C bus.
Edge-aligned with read data. Input with
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