MT8VDDT6464AY-335D3 Micron Technology Inc, MT8VDDT6464AY-335D3 Datasheet - Page 10

• Manufacturer Part Number: MT8VDDT6464AY-335D3
• Description: MODULE DDR 512MB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8VDDT6464AY-335D3

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184UDIMM
• Device Core Size: 64b
• Organization: 64Mx64
• Total Density: 512MByte
• Chip Density: 512Mb
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.4A
• Number Of Elements: 8
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
Table 9:
PDF: 09005aef80867ab3/Source: 09005aef80867a99
DD8C32_64x64A.fm - Rev. J 8/08 EN
Parameter/Condition
Operating one bank active-precharge current:
(MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and
control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2;
t
cycle
Precharge power-down standby current: All device banks idle; Power-down
mode;
Idle standby current: CS# = HIGH; All device banks idle;
CKE = HIGH; Address and other control inputs changing once per clock cycle;
V
Active power-down standby current: One device bank active; Power-down
mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active;
=
clock cycle; Address and other control inputs changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads; One device
bank active; Address and control inputs changing once per clock cycle;
(MIN); I
Operating burst write current: BL = 2; Continuous burst writes; One device
bank active; Address and control inputs changing once per clock cycle;
(MIN); DQ, DM, and DQS inputs changing twice per clock cycle
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank interleaving
reads; BL = 4 with auto precharge;
control inputs change only during active READ or WRITE commands
DD
CK =
IN
t
RAS (MAX);
= V
Specifications
t
CK (MIN); I
REF
t
t
OUT
CK =
CK =
for DQ, DM, and DQS
= 0mA
t
t
CK (MIN); CKE = LOW
CK (MIN); CKE = LOW
I
Values are shown for the
256Mb (32 Meg x 8) component data sheet
t
DD
CK =
OUT
Specifications and Conditions – 256MB (Die Revision ‘K’)
t
= 0mA; Address and control inputs changing once per clock
CK (MIN); DQ, DM, and DQS inputs changing twice per
t
RC =
MT46V32M8
t
RC (MIN);
256MB, 512MB (x64, SR) 184-Pin DDR SDRAM UDIMM
t
RC =
t
CK =
DDR SDRAM only and are computed from values specified in the
t
RC (MIN);
t
t
t
REFC =
REFC = 7.8125µs
CK (MIN); Address and
t
CK =
10
t
t
RC =
CK (MIN);
t
t
RC (MIN)
CK =
t
RC (MIN);
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
t
t
CK =
CK =
CK
t
t
t
RC
CK
CK
Symbol
I
I
I
I
I
I
I
DD
I
I
DD
DD
I
DD
I
I
DD
DD
DD
DD
DD
DD
DD
DD
4W
3N
5A
4R
2P
2F
3P
0
1
5
6
7
Electrical Specifications
©2003 Micron Technology, Inc. All rights reserved.
1,440
1,440
1,280
2,320
-40B
800
960
400
280
480
32
48
32
1,280
1,280
1,280
2,160
-335
720
920
400
240
440
32
48
32
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA