MT8VDDT6464HG-335D1 Micron Technology Inc, MT8VDDT6464HG-335D1 Datasheet - Page 13
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MT8VDDT6464HG-335D1
Manufacturer Part Number
MT8VDDT6464HG-335D1
Description
MODULE DDR SDRAM 512MB 200SODIMM
Manufacturer
Micron Technology Inc
Specifications of MT8VDDT6464HG-335D1
Memory Type
DDR SDRAM
Memory Size
512MB
Speed
167MHz
Package / Case
200-SODIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
200SODIMM
Device Core Size
64b
Organization
64Mx64
Total Density
512MByte
Chip Density
512Mb
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
1.4A
Number Of Elements
8
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
200
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
557-1127
Table 12: I
DDR SDRAM component values only
Notes: 1–5, 8, 10, 12, 47; notes appear on pages 18–21; 0°C
pdf: 09005aef8092973f, source: 09005aef80921669
DD8C16_32_64x64HG.fm - Rev. B 9/04 EN
PARAMETER/CONDITION
OPERATING CURRENT: One device bank; Active-Precharge;
t
once per clock cyle; Address and control inputs changing once
every two clock cycles
OPERATING CURRENT: One device bank; Active -Read Precharge;
Burst = 2;
control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks
idle; Power-down mode;
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;
t
once per clock cycle. V
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank
active; Power-down mode;
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device
bank; Active-Precharge;
t
cycle; Address and other control inputs changing once per clock
cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One
device bank active; Address and control inputs changing once per
clock cycle;
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once per
clock cycle;
twice per clock cycle
AUTO REFRESH CURRENT
SELF REFRESH CURRENT: CKE
OPERATING CURRENT: Four device bank interleaving READs (BL = 4)
with auto precharge,
control inputs change only during Active READ or WRITE
commands
RC =
CK MIN; CKE = HIGH; Address and other control inputs changing
CK =
t
t
RC (MIN);
CK (MIN); DQ, DM andDQS inputs changing twice per clock
t
RC =
t
t
CK =
CK =
t
RC (MIN);
t
DD
CK =
t
t
CK (MIN); I
CK (MIN); DQ, DM, and DQS inputs changing
Specifications and Conditions – 128MB
t
t
IN
RC =
CK (MIN); DQ, DM and DQS inputs changing
t
= V
RC =
t
CK =
t
CK =
t
t
REF
CK =
RC (MIN);
OUT
t
RAS (MAX);
t
0.2V
for DQ, DQS, and DM
t
CK (MIN); CKE = (LOW)
CK (MIN); I
= 0mA
t
CK (MIN); CKE = LOW
t
CK =
OUT
t
CK (MIN); Address and
t
t
REFC =
REFC = 15.625µs
= 0mA; Address and
t
RFC (MIN)
t
13
CK =
T
A
128MB, 256MB, 512MB (x64, SR)
+70°C; V
I
I
I
I
Micron Technology, Inc., reserves the right to change products or specifications without notice.
I
I
I
SYM
DD4W
DD3N
DD5A
I
I
DD2P
DD3P
DD4R
I
I
I
DD2F
DD0
DD1
DD5
DD6
DD7
DD
= V
DD
1,000
1,080
1,120
1,120
2,120
2,840
-335
360
200
400
24
40
24
200-PIN DDR SODIMM
Q = +2.5V ±0.2V
1,040
1,000
1,760
2,640
MAX
-262
880
960
360
200
400
24
40
24
©2004 Micron Technology, Inc. All rights reserved.
-26A/
1,000
1,760
2,600
-265
840
960
360
160
360
960
24
40
16
UNITS NOTES
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
21, 28,
21, 28,
20, 41
20, 41
20, 41
20, 41
24, 43
24, 43
20, 42
43
44
43
20
9