MT8VDDT6464HG-335D1 Micron Technology Inc, MT8VDDT6464HG-335D1 Datasheet - Page 12
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MT8VDDT6464HG-335D1
Manufacturer Part Number
MT8VDDT6464HG-335D1
Description
MODULE DDR SDRAM 512MB 200SODIMM
Manufacturer
Micron Technology Inc
Specifications of MT8VDDT6464HG-335D1
Memory Type
DDR SDRAM
Memory Size
512MB
Speed
167MHz
Package / Case
200-SODIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
200SODIMM
Device Core Size
64b
Organization
64Mx64
Total Density
512MByte
Chip Density
512Mb
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
1.4A
Number Of Elements
8
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
200
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
557-1127
Table 11:
PDF: 09005aef8092973f / Source: 09005aef80921669
DD8C32_64x64H.fm - Rev. D 9/08 EN
Parameter/Condition
Operating one bank active-precharge current:
t
cycle; Address and control inputs changing once every two clock
cycles
Operating one bank active-read-precharge current: BL = 4;
t
inputs changing once per clock cycle
Precharge power-down standby current: All device banks
idle; Power-down mode;
Idle standby current: CS# = HIGH; All device banks idle;
t
changing once per clock cycle; V
Active power-down standby current: One device bank active;
Power-down mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device
bank active;
inputs changing twice per clock cycle; Address and other control
inputs changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads;
One device bank active; Address and control inputs changing
once per clock cycle;
Operating burst write current: BL = 2; Continuous burst writes;
One device bank active; Address and control inputs changing
once per clock cycle;
changing twice per clock cycle
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank active interleave read current: Four device
bank interleaving reads (BL = 4) with auto precharge;
t
change only during active READ or WRITE commands
CK =
RC =
CK =
RC =
t
t
t
t
RC (MIN);
RC (MIN);
CK (MIN); DQ, DM, and DQS inputs changing once per clock
CK (MIN); CKE = HIGH; Address and other control inputs
t
RC =
I
Values are shown for the MT46V64M8 DDR SDRAM only and are computed from values specified in the
512Mb (64 Meg x 8) component data sheet
DD
t
t
CK =
CK =
t
Specifications and Conditions – 512MB
RAS (MAX);
t
CK =
t
t
CK =
CK =
t
t
CK (MIN); I
CK (MIN); Address and control inputs
t
CK =
t
t
t
CK (MIN); CKE = LOW
CK (MIN); I
CK (MIN); DQ, DM, and DQS inputs
t
t
IN
CK (MIN); CKE = LOW
CK =
OUT
= V
REF
t
CK (MIN); DQ, DM, and DQS
= 0mA; Address and control
OUT
for DQ, DM, and DQS
= 0mA
256MB, 512MB (x64, SR) 200-Pin DDR SDRAM SODIMM
t
t
RFC =
RFC = 7.8125µs
t
RC =
t
RFC (MIN)
t
RC (MIN);
12
Symbol
I
I
I
I
I
I
I
DD
DD
DD
I
I
DD
I
I
I
DD
DD
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
DD
DD
DD
DD
4W
3N
5A
4R
2P
2F
3P
0
1
5
6
7
1,240
1,480
1,520
1,560
2,760
3,600
-40B
440
360
480
40
88
40
Electrical Specifications
1,040
1,280
1,320
1,400
2,320
3,240
-335
360
280
400
40
80
40
©2004 Micron Technology, Inc. All rights reserved.
1,160
1,160
1,080
2,240
2,800
-265
920
320
240
360
40
80
40
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA