MT18LSDT3272AY-133G3 Micron Technology Inc, MT18LSDT3272AY-133G3 Datasheet - Page 9

• Manufacturer Part Number: MT18LSDT3272AY-133G3
• Description: MODULE SDRAM 256MB 168-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18LSDT3272AY-133G3

• Memory Type: SDRAM
• Memory Size: 256MB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

burst mode, and M10 and M11 are reserved for future
use. Address A12 (M12) is undefined but should be
driven LOW during loading of the mode register.
banks are idle, and the controller must wait the speci-
fied time before initiating the subsequent operation.
Violating either of these requirements will result in
unspecified operation.
Burst Length
ented, with the burst length being programmable, as
shown in Figure 5, Mode Register Definition Diagram,
on page 9. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 1, 2,
4, or 8 locations are available for both the sequential
and the interleaved burst types, and a full-page burst is
available for the sequential type. The full-page burst is
used in conjunction with the BURST TERMINATE
command to generate arbitrary burst lengths.
operation or incompatibility with future versions may
result.
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached, as shown in Table 7,
Burst Definition Table, on page 10. The block is
uniquely selected by A1–A9 when the burst length is
set to two; by A2–A9 when the burst length is set to
four; and by A3–A9 when the burst length is set to
eight. The remaining (least significant) address bit(s) is
(are) used to select the starting location within the
block. Full-page bursts wrap within the page if the
boundary is reached, as shown in Table 7, Burst Defini-
tion Table, on page 10.
Burst Type
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
09005aef807b3709
SD9_18C16_32x72AG.fm - Rev. E 6/04 EN
The mode register must be loaded when all device
Read and write accesses to the SDRAM are burst ori-
Reserved states should not be used, as unknown
When a READ or WRITE command is issued, a block
Accesses within a given burst may be programmed
128MB (x72, ECC, SR), 256MB (x72, ECC, DR)
9
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 7, Burst
Definition Table, on page 10.
to ensure compatibility
with future devices.
M11, M10 = “0, 0”
*Should program
The ordering of accesses within a burst is deter-
Figure 5: Mode Register Definition
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Reserved* WB
11
A11
10
A10
M9
0
1
168-PIN SDRAM UDIMM
9
A9
Op Mode
8
A8
7
A7
Programmed Burst Length
M8
Diagram
0
Single Location Access
-
CAS Latency
6
Write Burst Mode
A6
5
M7
A5
0
-
4
A4
M3
BT
M6-M0
Defined
0
1
3
A3
-
M2
M6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Burst Length
2
M1
M5
A2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
M0
M4
1
Operating Mode
Standard Operation
All other states reserved
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A1
©2004 Micron Technology, Inc.
0
A0
Reserved
Reserved
Reserved
Full Page
M3 = 0
Burst Type
Interleaved
Sequential
1
2
4
8
Mode Register (Mx)
Address Bus
Burst Length
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
M3 = 1
1
2
4
8