SDCFJ-512-388-03 SanDisk, SDCFJ-512-388-03 Datasheet - Page 62
![COMPACT FLASH 512MB](/photos/7/83/78343/mfg_sdcfj_series_sml.jpg)
SDCFJ-512-388-03
Manufacturer Part Number
SDCFJ-512-388-03
Description
COMPACT FLASH 512MB
Manufacturer
SanDisk
Datasheet
1.SDCFH-1024-388.pdf
(108 pages)
Specifications of SDCFJ-512-388-03
Memory Size
512MB
Memory Type
CompactFLASH
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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02/07, Rev. 12.0
ATA Command Description
Word 21: Buffer Size. This field defines the buffer capacity of 2 sectors or 1 kilobyte of
SRAM.
Word 22: ECC Count. This field defines the number of ECC bytes used on each sector in the
Read and Write Long commands.
Words 23-26: Firmware Revision. This field contains the revision of the firmware for this
product.
Words 27-46: Model Number. This field contains the model number for this product and is
left justified and padded with spaces (20h).
Word 47: Read/Write Multiple Sector Count. This field contains the maximum number of
sectors that can be read or written per interrupt using the Read Multiple or Write Multiple
commands.
Word 48: Double Word Support. This field indicates this product will not support double
word transfers.
Word 49: Capabilities. This field indicates if this product supports DMA Data transfers and
LBA mode. All SanDisk products support LBA mode.
Word 51: PIO Data Transfer Cycle Timing Mode. To determine the proper device timing
category, compare the Cycle Time specified in Table 3-15 with the contents of this field with
Table 3-14.
t
minimum command recovery time or command inactive time. The actual cycle time equals the
sum of the actual command active time and the actual command inactive time. The three
timing requirements of t
are greater than the sum of t
both t
IDENTIFY DEVICE data. A device implementation shall support any legal host
implementation.
The IORD-data tri-state parameter specifies the time from the negation edge of /IORD to the
time that the data bus is no longer driven by the device (tri-state).
Word 52: Single Word DMA Data Transfer Cycle Timing Mode. This field states this
product does not support any Single Word DMA data transfer mode.
0
NOTE
is the minimum total cycle time, t
2
: For backward compatibility with BIOS' written before Word 64 was
or t
defined for advanced modes, a device reports in Word 51 the highest
original PIO mode it can support (i.e., PIO mode 0, 1 or 2).
2i
to ensure that t
0
, t
2
2
0
, and t
and t
is equal to or greater than the value reported in the devices
5-8
2
2i
i. This means a host implementation may lengthen either or
2
shall be met. The minimum total cycle time requirements
is the minimum command active time, and t
SanDisk CompactFlash Card OEM Product Manual
© 2007 SanDisk Corporation
2i
is the
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