SDCFIF-002G-388 SanDisk, SDCFIF-002G-388 Datasheet - Page 39
SDCFIF-002G-388
Manufacturer Part Number
SDCFIF-002G-388
Description
COMPACT FLASH IND 2GB FIXED
Manufacturer
SanDisk
Datasheet
1.SDCFCF-001G-388.pdf
(97 pages)
Specifications of SDCFIF-002G-388
Memory Size
2GB
Memory Type
CompactFLASH
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
585-1233
SDCFIF-002G-388
SDCFIF-002G-388
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SanDisk Industrial Grade CompactFlash 5000
3.4.3
The Card Configuration and Status Register contain information about the
condition of the card
© 2007 SanDisk® Corporation
Conf5
D7
D6
D5
D2
D1
Operation
Read
Write
Bit
0
0
0
0
Card Configuration and Status Register (Address
202h in Attribute Memory)
Changed
SigChg
IOis8
PwrDwn
Int
Conf4
Name
0
0
0
0
Changed
0
D7
Conf3
.
Indicates that one or both of the Pin Replacement Register CRdy, or
CWProt bits are set to "1". When the Changed bit is set, -STSCHG Pin
46 is held low if the SigChg bit is a "1" and the card is configured for
the I/O interface.
The host sets and resets this bit to enable and disable a state-change
"signal" from the Status Register, the Changed bit control pin 46 the
Changed Status signal. If no state change signal is desired, this bit
should be set to zero "0" and pin 46 (-STSCHG) signal will be held high
while the card is configured for I/O
The host sets this bit to one "1" if the card is to be configured in an 8-bit
I/O mode. The card is always configured for both 8- and 16-bit I/O, so
this bit is ignored.
This bit indicates whether the host requests the card to be in the power
saving or active mode. When the bit is "1" the card enters a power
down mode. When "0", the host requests that the card enter the active
mode. The PCMCIA Rdy/-Bsy value becomes BUSY when this bit is
changed. Rdy/-Bsy will not become Ready until the power state
requested has been entered. The card automatically powers down
when it is idle and powers back up when it receives a command
This bit represents the internal state of the interrupt request. This value
is available whether or not I/O interface has been configured. This
signal remains true until the condition that caused the interrupt request
has been serviced. If interrupts are disabled by the -IEN bit in the
Device Control Register, this bit is a "0".
0
0
0
0
SigChg
SigChg
Conf2
D6
0
0
0
0
Table 26: Card Configurations
IOis8
IOis8
Conf1
D5
0
0
1
1
32
Conf0
0
0
0
1
0
1
D4
Description
Memory Mapped
I/O Mapped; any 16-byte system
decoded boundary
I/O Mapped; 1F0-1F7/3F6-3F7
I/O Mapped; 170-177/376-377
0
0
D3
Disk Card Mode
PwrDwn
PwrDwn
D2
Int
0
D1
0
0
D0
Product Manual
July 2007
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