SDCFCR-002G-388 SanDisk, SDCFCR-002G-388 Datasheet - Page 44

• Manufacturer Part Number: SDCFCR-002G-388
• Description: COMPACT FLASH IND 2GB
• Manufacturer: SanDisk
• Type: CompactFlashr

Specifications of SDCFCR-002G-388

• Memory Size: 2GB
• Memory Type: CompactFLASH
• Density: 2GByte
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Package Type: Not Required
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3.135/4.5V
• Operating Supply Voltage (max): 3.465/5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SanDisk Industrial Grade CompactFlash 5000
b.
4.2
When the system decodes a contiguous block of I/O registers to select a
CompactFlash Memory Card, the registers are accessed in the block of I/O
space decoded by the system as described in Table 32:
a.
b
© 2007 SanDisk® Corporation
address space of the Error and Feature byte-wide registers that lie at offset 1.
When accessed twice as byte register with CE1 low, the first byte to be accessed
is the even byte of the word and the second byte accessed is the odd byte of the
equivalent word access.
A byte access to register 0 with CE1 high and CE2 low accesses the error (read) or
feature (write) register.
Register 0 is accessed with -CE1 low and -CE2 low (and A0 = Do not care) as a
word register on the combined Odd Data Bus and Even Data Bus (D15-D0). This
register may also be accessed by a pairof byte accesses to the offset 0 with -CE1
low and -CE2 high. Note that the address space of thisword register overlaps the
address space of the Error and Feature byte-wide registers that lie at offset 1.
When accessed twice as byte register with CE1 low, the first byte to be accessed
is the even byte of the word and the second byte accessed is the odd byte of the
equivalent word access. A byte access to register 0 with CE1 high and CE2 low
accesses the error (read) or feature (write) register.
Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at
offset 0 and 1.
Register 8 is equivalent to register 0, while register 9 accesses the odd byte.
Therefore, if the registers are byte accessed in the order 9 then 8 the data will be
transferred odd byte then even byte. Repeated byte accesses to register 8 or 0
will access consecutive (even than odd) bytes from the data buffer. Repeated
word accesses to register 8, 9 or 0 will access consecutive words from the data
buffer. Repeated byte accesses to register 9 are not supported. However,
repeated alternating byte accesses to registers 8 then 9 will access consecutive
(even then odd) bytes from the data buffer. Byte accesses to register 9 access
only the odd byte of the data.
-REG
0
0
0
0
0
0
0
0
0
0
0
0
0
Contiguous I/O Mapped Addressing
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
0
1
1
Table 32: Contiguous I/O Decoding
A0
0
1
0
1
0
1
0
1
0
1
1
0
1
Offset
D
E
F
0
1
2
3
4
5
6
7
8
9
37
Even RD Data a
Error Register b
Sector Count
Sector No.
Cylinder Low
Cylinder High
Select Card/Head
Status
Dup Even RD Data b
Dup Odd RD Data b
Dup Error b
Alt Status
Drive Address
-IORD=0
Features b
Cylinder Low
Cylinder High
Select Card/Head
Command
Dup Features b
Device Ctl
Reserved
Even WR Data a
Sector Count
Sector No.
Dup Even WR Data b
Dup Odd WR Data b
-IOWR=0
Product Manual
July 2007