TH58512DC-T051(Y) Toshiba, TH58512DC-T051(Y) Datasheet
TH58512DC-T051(Y)
Specifications of TH58512DC-T051(Y)
TH58512DCT051Y
Related parts for TH58512DC-T051(Y)
TH58512DC-T051(Y) Summary of contents
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... It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. ...
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... The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. ...
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VALID BLOCKS (1) SYMBOL N Number of Valid Blocks VB (1) The TH58NS512 occasionally contains unusable blocks. Refer to Application Note (14) toward the end of this document. RECOMMENDED DC OPERATING CONDITIONS SYMBOL V Power Supply Voltage CC V High ...
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AC CHARACTERISTICS AND OPERATING CONDITIONS ( 0°~55° 3.3 V ± ± ± ± 0 SYMBOL t CLE Setup Time CLS t CLE Hold Time CLH t CE Setup Time ...
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Notes: (1) CE High to Ready time depends on the pull-up resistor tied to the (Refer to Application Note (7) toward the end of this document.) (2) Sequential Read is terminated when t If the delay is ...
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TIMING DIAGRAMS Latch Timing Diagram for Command/Address/Data CLE ALE I/O1 ~I/O8 Command Input Cycle Timing Diagram CLE t CLS ALS ALE I/O1 ~I/O8 Setup time CLH ...
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Address Input Cycle Timing Diagram t CLS CLE ALS ALE I/O1 ~I/O8 Data Input Cycle Timing Diagram CLE CE t ALS ALE WE I/O1 ~I/ ...
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Serial Read Cycle Timing Diagram REA I/O1 ~I/ Status Read Cycle Timing Diagram CLE t CLS I/O1 ~I/ ...
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Read Cycle (1) Timing Diagram CLE t t CLS CLH ALS t ALH ALE I/O1 00H A0~A7 ~I/O8 Column address ...
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Read Cycle (2) Timing Diagram CLE t t CLS CLH ALH ALS ALE I/O1 01H ~I/ Read Operation using 01H Command N: 0~255 ...
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Sequential Read (1) Timing Diagram CLE CE WE ALE RE I/O1 A0 00H ~A7 ~A16 ~I/O8 Column address Sequential Read (2) Timing Diagram CLE CE WE ALE RE I/O1 A0 01H ~A7 ~A16 ~I/O8 Column address ...
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Sequential Read (3) Timing Diagram CLE CE WE ALE RE I/O1 A0 50H ~A7 ~A16 ~I/O8 Column address A17 A25 ~A24 Page t 512 + 512 + R address Page ...
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Auto-Program Operation Timing Diagram t CLS CLE t t CLS CLH ALH t ALS ALE I/O1 A9 80H A0~A7 ~A16 ~I/O8 RY ...
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ID Read Operation Timing Diagram CLE t CLS ALH ALE I/O1 90H ~I/O8 t CLS ALS ALH AR1 t ...
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PIN FUNCTIONS The device is a serial access memory which utilizes time-sharing input of address information. The device pin-outs are configured as shown in Figure 1. Command Latch Enable: CLE The CLE input signal is used to control loading of ...
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Schematic Cell Layout and Address Assignment The Program operation works on page units while the Erase operation works on block units. 512 16 131072 pages 4096 blocks 528 Figure 2. Schematic Cell Layout Table 1. Addressing I/O8 I/O7 First cycle ...
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Table 3. Command table (HEX) First Cycle Serial Data Input 80 Read Mode (1) 00 Read Mode (2) 01 Read Mode (3) 50 Reset FF Auto Program 10 Auto Block Erase 60 Status Read 70 ID Read 90 Once the ...
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DEVICE OPERATION Read Mode (1) Read mode (1) is set when a 00H command is issued to the Command register. Refer to Figure 3 below for timing details and the block diagram. CLE CE WE ALE ...
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Read Mode (3) Read mode (3) has the same timing as Read modes (1) and (2) but is used to access information in the extra 16-byte redundancy area of the page. The start pointer is therefore set to a value ...
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Status Read The device automatically implements the execution and verification of the Program and Erase operations. The Status Read function is used to monitor the Ready/Busy status of the device, determine the result (pass/fail Program or Erase operation, ...
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Auto Page Program The device carries out an Automatic Page Program operation when it receives a 10H Program command after the address and data have been input. The sequence of command, address and data input is shown below. (Refer to ...
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Reset The Reset mode stops all operations. For example, in the case of a Program or Erase operation the internally generated voltage is discharged to 0 volts and the device enters Wait state. The address and data registers are set ...
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When a Status Read command (70H) is input after a Reset However, the following operation is prohibited. If the following operation is executed, correct resetting of the address and data register cannot be guaranteed ...
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ID Read The TH58NS512 contains ID codes which identify the device type and the manufacturer. The ID codes can be read out under the following timing conditions: CLE CE WE ALE RE I/O 90H ID Read command Address For the ...
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APPLICATION NOTES AND COMMENTS (1) Prohibition of unspecified commands The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is prohibited. Stored data may be corrupted if an unknown command is ...
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Acceptable commands after Serial Input command 80H Once the Serial Input command 80H has been input, do not input any command other than the Program Execution command 10H or the Reset command FFH Address input RY / ...
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termination for the Ready/Busy pin ( A pull-up resistor needs to be used for termination because the circuit Device V SS Figure 19. This data may vary from device to device. ...
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Note regarding the WP signal The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming WE DIN (100 ns min) WW Disable ...
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When four address cycles are input Although the device may read in a fourth address ignored inside the chip. Read operation CLE CE WE ALE I/O 00H, 01H, 50H Internal read operation starts when ...
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Several programming cycles on the same page (Partial Page Program) A page can be divided into segments. Each segment can be programmed individually as follows: First programming Data Pattern 1 Second programming All 1s Tenth programming ...
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Invalid blocks (bad blocks) The device contains unusable blocks. Therefore, the following issues must be recognized: Bad Block Bad Block Figure 26. (15) Failure phenomena for Program and Erase operations The device may fail during a Program or Erase ...
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... Avoid touching the connectors avoid damage from static electricity. This card should be kept in the antistatic film case when not in use. (3) Toshiba cannot accept, and hereby disclaims liability for, any damage to the card including data corruption that may occur because of mishandling. How to read out unique ID number The 128 bit unique ID number is embedded in the device ...
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PACKAGE DIMENSIONS • FDC-22C TH58NS512DC Unit: mm 2000-08-27 33/33 ...