TH58NS100DC Toshiba, TH58NS100DC Datasheet
TH58NS100DC
Specifications of TH58NS100DC
TH58NS100DC-TO51
TH58NS100DCTO51
Related parts for TH58NS100DC
TH58NS100DC Summary of contents
Page 1
... The TH58NS100DC is a SmartMedia device. This unique ID number is applicable to image files, music files, electronic books, and so on where copyright protection is required. The data stored in the TH58NS100DC needs to comply with the data format standardized by the SSFDC Forum in order to maintain compatibility with other SmartMedia FEATURES Organization • ...
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... The information contained herein is subject to change without notice. Status register Address register Command register Control circuit HV generator PARAMETER PARAMETER CONDITION OUT TH58NS100DC Column buffer Column decoder Data register Sense amp Memory cell array extended area (embedded ID) RATING −0.6 to 4.6 −0.6 to 4.6 − ...
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... IL OUT cycle = cycle = cycle = cycle − 0 −400 µ 2 0 pin V OL TH58NS100DC MIN TYP. MAX 8032 8192 MIN TYP. MAX 3.0 3.3 3.6 + 0.3 2 −0.3* 0.8 MIN TYP. MAX ±10 ± ...
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... CE High to Ready (When interrupted Read Mode) CRY t Device Reset Time (Read/Program/Erase) RST AC TEST CONDITIONS PARAMETER Input level Input pulse rise and fall time Input comparison level Output data comparison level Output load PARAMETER TH58NS100DC MIN MAX UNIT ...
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... Refer to Application Note (12) toward the end of this document. is greater than or equal to 100 ns. If the CEH signal stays Ready. t CEH 526 527 A Busy MIN TH58NS100DC pin. ≥ 100 → Busy signal is not output CRY ( 0° to 55° 3.3 V ± ± ± ± 0 TYP. MAX UNIT µ ...
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... TIMING DIAGRAMS Latch Timing Diagram for Command/Address/Data CLE ALE I/O1 to I/O8 Command Input Cycle Timing Diagram CLE t CLS ALS ALE I/O1 to I/O8 Setup Time CLH ALH TH58NS100DC Hold Time 2001-03-21 6/43 ...
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... Address Input Cycle Timing Diagram t CLS CLE ALS ALE I/O1 to I/O8 Data Input Cycle Timing Diagram CLE CE t ALS ALE WE I/ A16 TH58NS100DC ALH A17 to A24 A25 to A26 : CLH 527 2001-03-21 7/43 ...
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... Serial Read Cycle Timing Diagram REA I/ Status Read Cycle Timing Diagram CLE t CLS I/ 70H represents the hexadecimal number REH RHZ REA RHZ t CLS t CLH WHC CSTO t WHR 70H* TH58NS100DC CHZ REA RHZ t CHZ RSTO RHZ Status output : 2001-03-21 8/43 ...
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... Column address Read operation using 00H command 255 t t ALH AR2 A17 A25 to A24 to A26 t t ALH AR2 A17 A25 to A24 to A26 TH58NS100DC REA OUT OUT OUT OUT 527 : CHZ RHZ t t REA OUT OUT OUT 2001-03-21 9/43 t CEH t CRY t RB ...
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... DH I/O1 50H to I/O8 Column address Read operation using 50H command ALH A17 A25 A16 to A24 to A26 N* t ALH A17 A25 A16 to A24 to A26 N* TH58NS100DC t AR2 REA D D OUT OUT 256 + N 256 + AR2 REA D D OUT OUT 512 + N 512 + 2001-03-21 10/43 D OUT ...
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... CE WE ALE RE I/O1 A0 01H to to I/O8 A7 Column address A17 A25 A16 A24 A26 Page t R address M Page M access A9 A17 A25 A16 A24 A26 Page t 256 + 256 + R address Page M access TH58NS100DC 527 Page access : 527 256 + Page access : 2001-03-21 11/43 527 527 ...
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... Sequential Read (3) Timing Diagram CLE CE WE ALE RE I/O1 A0 50H I/O8 Column address A17 A25 A16 A24 A26 Page t 512 + 512 + R address Page M access TH58NS100DC 527 512 513 514 t 512 + Page access : 2001-03-21 12/43 527 ...
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... IN to A24 to A26 : not input data while data is being output ALH WB BERASE A25 D0H to A26 Erase Start Busy command : not input data while data is being output TH58NS100DC t PROG 10H 70H 527 Status output 70H Status output Status Read command 2001-03-21 13/43 ...
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... CLS CLH ALH t ALS ALE I/ 80H /O8 to A16 ALH t ALS A17 A25 A26 to A24 Max 3 times repeat 31 times repeat (Page programming in multi block) Max 4 blocks programming TH58NS100DC t DBSY t WB 11H 80H D 527 IN Auto program (dummy) Last district input 2 2001-03-21 14/ ...
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... Do not input data while data is being output. times repeat 2 t ALH t ALS A17 A25 A26 to A24 Auto program (multi block program) Last district input 31 times repeat (Page programming in multi block) Max 4 blocks programming TH58NS100DC t MBPBSY t WB 15H 80H D 527 IN 3 Max 3 times repeat 2001-03-21 15/ ...
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... A7 to I/O8 to A16 not input data while data is being output ALH t ALS A17 A25 A26 to A24 Max 3 times repeat (Last pages programming in multi block) Max 4 blocks programming TH58NS100DC t DBSY t WB 11H 80H D 527 IN Auto program (dummy) 4 Last district input 2001-03-21 16/ ...
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... Do not input data while data is being output. 4 Max 3 times repeat t ALH t ALS A17 A25 A26 to A24 Last district input (Last pages programming in multi block) Max 4 blocks programming TH58NS100DC t Prog 10H 71H D 527 IN Auto program (true) 5 Status read 2001-03-21 17/43 Status output ...
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... WE t ALS ALE I/ A17 to 60H A16 A24 to I/O8 Auto Block Erase Setup command Max 4 times repeat : not input data while data is being output ALH WB BERASE A25 to D0H A26 Erase Start Busy command TH58NS100DC 71H Status output Status Read command 2001-03-21 18/43 ...
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... ID Read (2) Operation Timing Diagram CLE t CLS t CLS ALH ALS ALE I/O1 91H to I/ ALH AR1 t REAID 00 98H Address Maker code input ALH AR1 t REAID 00 21H Address input TH58NS100DC REAID REAID REAID 79H A5H C0H Device code Option code (1) Option code ( 2001-03-21 19/43 ...
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... after completion of the operation. The output buffer for this signal is an open drain. Low Voltage Detect: LVD The LVD signal is used to detect the power supply voltage level L), such as during a Program or Erase operation, and will not enter REA TH58NS100DC CLE ALE WE WP ...
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... Table 1. 8I/O I/O6 I/O5 I/O4 I/O3 I/ A14 A13 A12 A11 A10 A22 A21 A20 A19 A18 A26 * CLE ALE TH58NS100DC I/ Column address A26 : Page address A9 A14 to A26 : Block address A9 to A13 : NAND address in block A17 A25 2001-03-21 21/ ...
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... Second Cycle Acceptable while Busy D0 ALE TH58NS100DC HEX data bit assignment (Example) Serial Data Input: 80H I/ I/O1 I/O1 to I/O8 Power L Output Active H High impedance Active High impedance Standby * 2001-03-21 22/43 ...
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... The operation of the device after input of the 01H command is the same as that of Read mode (1). If the start pointer set after column address 256, use Read mode (2). However, for a Sequential Read, output of the next page Cell array starts from column address 0. TH58NS100DC 2001-03-21 23/43 ...
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... A4-to-A7 address. (A “00H” command is necessary to move the pointer back to the 0-to-511 main memory cell location.) Data output t R Busy Busy (01H) 256 527 A Sequential Read (2) TH58NS100DC Data output Busy (50H) 512 527 A Sequential Read (3) 2001-03-21 24/43 ...
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... Device 2 3 Busy 70H Status on Device 1 Figure 6. Status Read timing application example pin signals from multiple devices are wired together as shown in the TH58NS100DC The Pass/Fail status on I/O1 is only valid when the device is in the Ready state Device N Status on Device N 2001-03-21 25/ ...
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... After programming, the programmed data is transferred back to the register to be automatically verified by the device. If the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. D0 Busy TH58NS100DC Pass 70 I/O Status Read Fail command ...
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... Dummy Data input Program command command Address Data input Address input 0 to 527 input (District 1) (District 2) TH58NS100DC Dummy Multi block Data input Program Program command command command Data input Address Data input 0 to 527 input 0 to 527 11 80 ...
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... Pass: 0 Fail: 1 Pass: 0 Fail: 1 Pass: 0 Fail: 1 Pass: 0 Fail not care Ready: 1 Busy: 0 Protect: 0 Not Protect: 1 TH58NS100DC I/O1 describes total Pass/Fail condition least one fail occurred in 32 times × 4 (512 + 16 byte) page write operation, it shows “Fail” condition. I/O2 describes total Pass/Fail condition. ...
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... Status Read operation Untill the Ready condition after the programming terminated by “10H” command, effective bit in the Status data is limited on Ready/Busy bit. In other words, Pass/Fail condition can be checked only in the Ready condition after “10H” command. TH58NS100DC 2001-03-21 29/43 ...
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... Fail: 1 Pass: 0 Fail not care Ready: 1 Busy: 0 Protect: 0 Not Protect: 1 TH58NS100DC I/O1 describes total Pass/Fail condition least one fail occurred in Max 4 Blocks erase operation, it shows “Fail” condition. I/O2 describes Pass/Fail condition. If fail occurred in District 0 area, it shows “Fail” condition. I/O3, I/O4 and I/O5 are as same manner as I/O2 ...
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... The second FF (max 10 µs) t RST (max 6 µs) t RST command is invalid, but the third TH58NS100DC Figure 8. 00 Figure 9. 00 (max 500 µs) RST Figure 10. 00 Figure 11. I/O status: Pass/Fail → Pass Ready/Busy → Ready I/O status: Ready/Busy → Busy Figure 12. ( command is valid ...
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... CR t AR1 t REAID 98H Maker code , t and t refer to the AC Characteristics. REAID CR AR1 Figure 13. ID Read timing I/O7 I/O6 I/O5 I/ TH58NS100DC 79H A5H Device code Option code (1) Option code (2) I/O3 I/O2 I/O1 Hex Data 98H 79H A5H C0H** 2001-03-21 32/43 C0H ...
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... For the specifications of the access times t Table 7. ID Codes read out by command 91H I/O8 I/O7 Extended ID code AR1 t REAID 21H Extended ID code , t and t refer to the AC Characteristics. REAID CR AR1 Figure 14. ID Read timing I/O6 I/O5 I/O4 I/ TH58NS100DC I/O2 I/O1 Hex Data 0 1 21H 2001-03-21 33/43 ...
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... V and CE signal is kept high Operation Figure 15. Power-on/off Sequence becomes 2 recommends starting access after about CC FF Reset Figure 16. 10 For this operation the “FFH” command is needed. TH58NS100DC Don’t care V IL 2001-03-21 34/43 ...
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... Read mode. In this case, data output starts automatically from address N and address input is unnecessary Ex.) Random page program (Prohibition) DATA IN: Data (1) Page 0 (1) Page 1 (2) (3) Page 2 Page 15 Page 31 Figure 17. page programming within a block 70 Status Read command input Figure 18. TH58NS100DC Data (32) Data register (2) (16) (3) (1) (32) 00 [A] Status Read Status output 2001-03-21 35/43 ...
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... C area C area Add Start point B area A area Add DIN Start point C Area Add DIN Start point B Area Figure 20. Example of How to Set the Pointer TH58NS100DC 255 256 511 512 A B Pointer control Figure 19. Pointer control 50H Add Start point C area 00H Add ...
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... This data may vary from device to device. We recommend that you use this data as a reference when selecting a resistor value Ready 1.5 µs 1.0 µ 0.5 µ KΩ TH58NS100DC buffer consists of an open drain 3.0 V Busy 1 3 25° 100 KΩ 3 KΩ 4 KΩ ...
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... The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming WE DIN (100 ns min) WW Disable Programming WE DIN (100 ns min) WW Enable Erasing WE DIN (100 ns min) WW Disable Erasing WE DIN (100 ns min TH58NS100DC 2001-03-21 38/43 ...
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... Although the device may read in a fifth address ignored inside the chip. Read operation CLE CE WE ALE I/O 00H, 01H or 50H Program operation CLE CE WE ALE I/O 80H Address input WE Internal read operation starts when WE goes High in the fourth cycle. Figure 22. Address input ignored Figure 23. TH58NS100DC ignored Data input 2001-03-21 39/43 ...
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... Busy state. (Refer to Figure 25.) I/O 00H/01H/50H Hence the RE clock input must start after the address input. All 1s Data Pattern 2 All 1s Data Pattern 2 Figure 24. Address input Figure 25. TH58NS100DC All 1s Data Pattern 3 Data Pattern 3 2001-03-21 40/43 ...
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... When an error happens in Block A, try to reprogram the data into another (Block B) by loading from an external buffer. Then, prevent Block A further system accesses to Block A (by creating a bad block table or by using an another appropriate scheme). Block B Figure 27. TH58NS100DC TYP. MAX UNIT 8192 Block TM . ...
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... Some electrical specifications in this data sheet show differences from the Forum’s electrical specification. Complying with the Forum’s electrical specification maintains compatibility with other SmartMedias. Please refer following SSFDC Forum’s URL to get the detailed information of each specification. URL http://www.ssfdc.or. especially with large capacity SmartMedia TH58NS100DC small removable TM . 2001-03-21 42/43 ...
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... PACKAGE DIMENSIONS Weight: 2.2 g (typ.) TH58NS100DC 2001-03-21 43/43 ...