DS1982-F3+ Maxim Integrated Products, DS1982-F3+ Datasheet - Page 13

• Manufacturer Part Number: DS1982-F3+
• Description: IBUTTON 1KBit ADD-ONLY F3
• Manufacturer: Maxim Integrated Products
• Series: iButton®r

Specifications of DS1982-F3+

• Rohs Information: IButton RoHS Compliance Plan
• Memory Size: 128B
• Memory Type: EPROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS1982
significant byte of the new 2-byte address will also be loaded into the 8-bit CRC generator as a starting
value. The bus master will issue the next byte of data using eight write time slots.
As the DS1982 receives this byte of data into the scratchpad, it also shifts the data into the CRC generator
that has been preloaded with the LSB of the current address, and the result is an 8-bit CRC of the new
data byte and the LSB of the new address. After supplying the data byte, the bus master will read this
8-bit CRC from the DS1982 with eight read time slots to confirm that the address incremented properly
and the data byte was received correctly. If the CRC is incorrect, a Reset Pulse must be issued and the
Write Memory command sequence must be restarted. If the CRC is correct, the bus master will issue a
programming pulse and the selected byte in memory will be programmed.
Note that the initial pass through the Write Memory flow chart will generate an 8-bit CRC value that is
the result of shifting the command byte into the CRC generator, followed by the 2 address bytes, and
finally the data byte. Subsequent passes through the Write Memory flow chart due to the DS1982
automatically incrementing its address counter will generate an 8-bit CRC that is the result of loading (not
shifting) the LSB of the new (incremented) address into the CRC generator and then shifting in the new
data byte.
For both of these cases, the decision to continue (to apply a program pulse to the DS1982) is made
entirely by the bus master, since the DS1982 will not be able to determine if the 8-bit CRC calculated by
the bus master agrees with the 8-bit CRC calculated by the DS1982. If an incorrect CRC is ignored and a
program pulse is applied by the bus master, incorrect programming could occur within the DS1982. Also
note that the DS1982 will always increment its internal address counter after the receipt of the eight read
time slots used to confirm the programming of the selected EPROM byte. The decision to continue is
again made entirely by the bus master; therefore if the EPROM data byte does not match the supplied
data byte but the master continues with the Write Memory command, incorrect programming could occur
within the DS1982. The Write Memory command sequence can be exited at any point by issuing a Reset
Pulse.
WRITE STATUS [55h]
The Write Status command is used to program the EPROM Status data field. The bus master will follow
the command byte with a 2-byte starting address (TA1=(T7:T0), TA2=(T15:T8)) and a byte of status data
(D7:D0). An 8-bit CRC of the command byte, address bytes, and data byte is computed by the DS1982
and read back by the bus master to confirm that the correct command word, starting address, and data
byte were received.
If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must
be repeated. If the CRC received by the bus master is correct, a programming pulse (12 volts on the 1-
Wire bus for 480 s) is issued by the bus master. Prior to programming, the first 7 bytes of the EPROM
Status data field will appear as logical 1s. For each bit in the data byte provided by the bus master that is
set to a logical 0, the corresponding bit in the selected byte of the EPROM Status data field will be
th
programmed to a logical 0 after the programming pulse has been applied at that byte location. The 8
byte of the EPROM status byte data field is factory-programmed to contain 00h.
After the 480 s programming pulse is applied and the data line returns to a 5-volt level, the bus master
issues eight read time slots to verify that the appropriate bits have been programmed. The DS1982
responds with the data from the selected EPROM Status address sent least significant bit first. This byte
contains the logical AND of all bytes written to this EPROM Status Byte address. If the EPROM Status
Byte contains 1s in bit positions where the byte issued by the master contained 0s, a Reset Pulse should
be issued and the current byte address should be programmed again. If the DS1982 EPROM Status Byte
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