HCPL-5121-100 Avago Technologies US Inc., HCPL-5121-100 Datasheet - Page 7

• Manufacturer Part Number: HCPL-5121-100
• Description: ISOLAT 1.5KVDC 1CH TOTEM 8SMD BJ
• Manufacturer: Avago Technologies US Inc.

Specifications of HCPL-5121-100

• Output Type: Push-Pull, Totem-Pole
• Package / Case: 8-SMD Butt Joint
• Voltage - Isolation: 1500VDC
• Number Of Channels: 1, Unidirectional
• Current - Output / Channel: 2A
• Propagation Delay High - Low @ If: 300ns @ 10mA ~ 18mA
• Current - Dc Forward (if): 25mA
• Input Type: DC
• Mounting Type: Surface Mount
• Configuration: 1 Channel
• Maximum Propagation Delay Time: 500 ns
• Maximum Forward Diode Voltage: 1.8 V
• Minimum Forward Diode Voltage: 1.2 V
• Maximum Reverse Diode Voltage: 5 V
• Maximum Forward Diode Current: 18 mA
• Maximum Power Dissipation: 295 mW
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 55 C
• Number Of Elements: 1
• Forward Voltage: 1.8V
• Forward Current: 25mA
• Package Type: PDIP
• Operating Temp Range: -55C to 125C
• Power Dissipation: 295mW
• Propagation Delay Time: 500ns
• Pin Count: 8
• Mounting: Surface Mount
• Reverse Breakdown Voltage: 5V
• Operating Temperature Classification: Military
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

Package Characteristics
Over recommended operating conditions (T
*All typicals at T
Notes:
. Maximum pulse width = 0 µs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with I
2. Maximum pulse width = 50 µs, maximum duty cycle = 0.5%.
3. In this test V
4. Maximum pulse width =  ms, maximum duty cycle = 20%.
5. This is a momentary withstand test, not an operating condition.
6. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together.
. The difference between t
8.
9.
0. Common mode transient immunity in a low state is the maximum tolerable dV
. This load condition approximates the gate load of a 200 V/5A IGBT.
2. Pulse Width Distortion (PWD) is defined as |t
3. Standard parts receive 00% testing at 25°C (Subgroups  and 9). SMD and Class H parts receive 00% testing at 25, 25, and -55°C (Sub
4. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed to limits

Parameter
Input-Output
Leakage Current
Resistance
(Input-Output)
Capacitance
(Input-Output)
peak minimum = 2.0 A. See Applications section for additional details on limiting I
output will remain in the high state (i.e., V
output will remain in a low state (i.e., V
Pins  and 4 need to be connected to LED common.
Common mode transient immunity in the high state is the maximum tolerable dV
groups  and 9, 2 and 0, 3 and , respectively).
specified for all lots not specifically tested.
OH
is measured with a dc load current. When driving capacitive loads V
A
= 25°C.
Symbol
R
C
I
PHL
I-O
I-O
I-O
and t
PLH
V
I-O
between any two HCPL-520 parts under the same test condition.
t = 5 sec., T
= 1500Vdc, RH
O
Test Conditions
< .0 V).
V
I-O
O
f = 1 MHz
> 5.0 V).
= 500 V
PHL
-t
A
PLH
= 25°C
| for any given device.
A
DC
≤
= -55 to +25°C) unless otherwise specified.
65%,
Subgroups (13)
Group A
1
CM
/dt of the common mode pulse, V
OH
OH
CM
will approach V
/dt of the common mode pulse, V
Min.
peak.
Limits
Typ.*
10
2.5
10
CC
as I
OH
Max.
1.0
approaches zero amps.
CM
Units
, to assure that the
µA
Ω
pF
CM
, to assure that the
Fig
Note
5, 6
O
6
6