HCPL-5150 Avago Technologies US Inc., HCPL-5150 Datasheet
HCPL-5150
Specifications of HCPL-5150
Related parts for HCPL-5150
HCPL-5150 Summary of contents
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... The voltage and current supplied by this opto- coupler makes it ideally suited for directly driving IGBTs with ratings up to 1200 V/50 A. For IGBTs with higher ratings, the HCPL-5150 can be used to drive a discrete power stage, which drives the IGBT gate. The products are capable of operation and storage over the full military temperature range and can be purchased as either commercial product, with full MIL-PRF-38534 ...
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... MAX. 2.79 (0.110) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). Selection Guide Lead Configuration Options Avago Part Number and Options Commercial HCPL-550 MIL-PRF-38534, Class H HCPL-55 Standard Lead Finish Gold Plate Solder Dipped * Option -00 Butt Cut/Gold Plate Option -00 Gull Wing/Soldered * Option -300 * Solder contains lead ...
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Hermetic Optocoupler Options Option Description 00 Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on commercial and hi-rel product (see drawings below for details). 0.51 (0.020) MIN. 2.29 (0.090) 2.79 (0.110) 00 Lead ...
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Absolute Maximum Ratings Parameter Symbol Storage Temperature Operating Temperature Case Temperature Junction Temperature Lead Solder Temperature Average Input Current Peak Transient Input Current (< ms pulse width, 300 pps) Reverse Input Voltage “High” Peak Output Current I OH (PEAK) “Low” ...
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Electrical Specifications (DC) Over recommended operating conditions ( Ground) unless otherwise specified. EE Parameter Symbol High Level Output Current I OH Low Level Output Current I OL High Level Output Voltage V OH Low Level Output Voltage V OL High Level Supply Current I CCH Low ...
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Switching Specifications (AC) Over recommended operating conditions ( Ground) unless otherwise specified. EE Parameter Symbol Propagation Delay Time t PLH to High Output Level Propagation Delay Time t PHL to Low Output Level Pulse Width Distortion PWD Propagation Delay Difference PDD Between Any Two Parts (t ...
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... In this test V is measured with a dc load current. When driving capacitive loads Maximum pulse width = 1 ms, maximum duty cycle = 20%. 5. This is a momentary withstand test, not an operating condition. 6. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together. 7. The difference between t and t between any two HCPL-5150 parts under the same test condition. PHL PLH 8. Pins 1 and 4 need to be connected to LED common. 9. Common mode transient immunity in the high state is the maximum tolerable |dV output will remain in the high state (i.e., V 10. Common mode transient immunity in a low state is the maximum tolerable |dV will remain in a low state (i.e., V < 1.0 V). ...
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18mA 100 30V -60 - 120 150 TEMPERATURE - C ...
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10mA 25˚ PLH 47Ω 3nF, PHL g g Duty Cycle = 50 10kHz 400 300 200 100 SUPPLY VOLTAGE ...
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Figure 17. I Test Circuit Figure 19. V Test Circuit ...
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500 Ω KHz 50% DUTY 3 CYCLE < Figure 23 and t Test ...
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... Applications Information Eliminating Negative IGBT Gate Drive To keep the IGBT firmly off, the HCPL-5150 has a very low maximum V specification of 1.0 V. The HCPL-5150 OL realizes this very low V by using a DMOS transistor OL with 4 W (typical) on resistance in its pull down circuit. When the HCPL-5150 is in the low state, the IGBT gate ...
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... Switching Frequency 100 250 500 100 Rg - GATE RESISTANCE - Ω Figure 27. Energy Dissipated in the HCPL-5150 for Each IGBT Switching Cycle 0.1 µ LED Drive Circuit Considerations for Ultra High CMR Perfor- mance. Without a detector shield, the dominant cause of opto- coupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure 28 ...
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... Figure 32. Recommended LED Drive Circuit for Ultra-High CMR F IPM Dead Time and Propagation Delay Specifications. and SAT The HCPL-5150 includes a Propagation Delay Difference (PDD) specification intended to help designers minimize , the F(OFF) “dead time” in their power inverter designs. Dead time is the time period during which both the high and low side power transistors (Q1 and Q2 in Figure 25) are off ...
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I LED1 V OUT1 OFF V OUT2 I LED2 t PHL MAX t PLH MIN PDD* MAX = ( PHL PLH MAX PHL MAX Figure 33. Minimum LED Skew for Zero Dead ...
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... UVLO– UVLO– pler output will go into the low state with a typical delay, UVLO Turn Off Delay, of 0.6 ms. When the HCPL-5150 output is in the low state and the supply voltage rises above the HCPL-5150 V threshold (11.0 < V < 13.5) the optocoupler output UVLO+ will go into the high state (assuming LED is “ON”) with a typical delay, UVLO Turn On Delay of 0 ...