HCPL-5430 Avago Technologies US Inc., HCPL-5430 Datasheet - Page 11
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HCPL-5430
Manufacturer Part Number
HCPL-5430
Description
OPTOCOUPLER 2CH 40MBS 8-DIP
Manufacturer
Avago Technologies US Inc.
Datasheet
1.HCPL-5400.pdf
(12 pages)
Specifications of HCPL-5430
Package / Case
8-DIP (0.300", 7.62mm)
Voltage - Isolation
1500VDC
Number Of Channels
1, Unidirectional
Current - Output / Channel
25mA
Data Rate
40Mbps
Propagation Delay High - Low @ If
33ns @ 10mA
Current - Dc Forward (if)
10mA
Input Type
DC
Output Type
Push-Pull, Totem-Pole
Mounting Type
Through Hole
Maximum Continuous Output Current
25 mA
Maximum Fall Time
10 ns
Maximum Forward Diode Current
10 mA
Maximum Rise Time
15 ns
Minimum Forward Diode Voltage
1 V
Output Device
Logic Gate Photo IC
Configuration
2 Channel
Maximum Baud Rate
40 MBps
Maximum Forward Diode Voltage
1.85 V
Maximum Reverse Diode Voltage
3 V
Maximum Power Dissipation
200 mW
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 55 C
Number Of Elements
2
Baud Rate
40Mbps
Forward Voltage
1.85V
Forward Current
10mA
Output Current
25mA
Package Type
PDIP
Operating Temp Range
-55C to 125C
Power Dissipation
200mW
Propagation Delay Time
60ns
Pin Count
8
Mounting
Through Hole
Reverse Breakdown Voltage
3V
Operating Temperature Classification
Military
Lead Free Status / RoHS Status
Lead free by exemption / RoHS compliant by exemption
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free by exemption / RoHS compliant by exemption
Available stocks
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MIL-PRF-38534 Class H, Class K, and
DSCC SMD Test Program
Avago Technologies’ Hi-Rel Optocouplers are in
compliance with MIL-PRF-38534 Classes H and K. Class
H and Class K devices are also in compliance with DSCC
drawings 5962-89570, and 5962-89571.
Testing consists of 100% screening and quality
conformance inspection to MIL-PRF-38534.
Data Rate and Pulse-Width Distortion Definitions
Propagation delay is a figure of merit which describes
the finite amount of time required for a system to
translate information from input to output when shifting
logic levels. Propagation delay from low to high (t
specifies the amount of time required for a system’s
output to change from a Logic 0 to a Logic 1, when
Applications
Figure 13. Recommended HCPL-5400 interface circuit
11
DATA
IN
A
GND 1
V
CC1
= +5 V
1
TOTEM
POLE
OUTPUT GATE
(e.g. 54AS1000)
226
274
30 pF
HCPL-5400
Y = A
GND
V
CC
0.1 µF
TTL
LSTTL
STTL
HCMOS
PLH
)
2
V
CC2
given a stimulus at the input. Propagation delay from
high to low (t
for a system’s output to change from a Logic 1 to a
Logic 0, when given a stimulus at the input (see
Figure 5).
When t
results. Pulse width distortion is defined as |t
and determines the maximum data rate capability of a
distortion-limited system. Maximum pulse width
distortion on the order of 25-35% is typically used when
specifying the maximum data rate capabilities of
systems. The exact figure depends on the particular
application (RS-232, PCM, T-1, etc.).
These high performance optocouplers offer the
advantages of specified propagation delay (t
and pulse width distortion (|t
and power supply voltage ranges.
DATA
OUT
Y
GND 2
= 5 V
PLH
and t
PHL
PHL
) specifies the amount of time required
differ in value, pulse width distortion
PLH
-t
PHL
|) over temperature
PLH
PHL
, t
- t
PHL
PLH
),
|