HCPL-5200#200 Avago Technologies US Inc., HCPL-5200#200 Datasheet - Page 10
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HCPL-5200#200
Manufacturer Part Number
HCPL-5200#200
Description
OPTOCOUPLER 1CH LO IF GOLD 8-DIP
Manufacturer
Avago Technologies US Inc.
Datasheet
1.HCPL-5200.pdf
(14 pages)
Specifications of HCPL-5200#200
Package / Case
8-DIP (0.300", 7.62mm)
Voltage - Isolation
1500VDC
Number Of Channels
1, Unidirectional
Current - Output / Channel
15mA
Data Rate
5MBd
Propagation Delay High - Low @ If
173ns @ 2mA
Current - Dc Forward (if)
8mA
Input Type
DC
Output Type
Tri-State
Mounting Type
Through Hole
Maximum Continuous Output Current
15 mA
Maximum Fall Time
10 ns
Maximum Forward Diode Current
8 mA
Maximum Rise Time
45 ns
Minimum Forward Diode Voltage
1 V
Output Device
Logic Gate Photo IC
Configuration
1 Channel
Maximum Baud Rate
5 MBps
Maximum Forward Diode Voltage
1.8 V
Maximum Reverse Diode Voltage
3 V
Maximum Power Dissipation
200 mW
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 55 C
Lead Free Status / RoHS Status
Lead free by exemption / RoHS compliant by exemption
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Typical Characteristics
�ll t���ical value� are at �
Note���
�. Peak �orward �n�ut Current �ul�e width < �0 �� at � ���z ma�imum re�etition rate.
�. Each channel o� a multichannel device.
�. Duration o� out�ut �hort circuit time not to e�ceed �0 m�.
��. �ll device� are con�idered two�terminal device��� mea�ured between all in�ut lead� or terminal� �horted together and all out�ut lead� or ter�
�. �hi� i� a momentar�� with�tand te�t�� not an o�erating condition.
6. CM
7. t
�. Mea�ured between each in�ut �air �horted together and all out�ut connection� �or that channel �horted together.
9. Mea�ured between adjacent in�ut �air� �horted together �or each multichannel device.
�0. Zero�bia� ca�acitance mea�ured between the �ED anode and cathode.
��. Standard �art� receive �00% te�ting at ���C (Subgrou�� � and 9). SMD�� Cla�� �� and Cla�� � �art� receive �00% te�ting at ���� ����� and –���C
��. Parameter� are te�ted a� �art o� device initial characterization and a�ter de�ign and �roce�� change�. Parameter� guaranteed to limit� ��eci�
10
Parameter
�n�ut Current �����tere�i�
�n�ut Diode �em�erature
Coefficient
�e�i�tance (�n�ut��ut�ut)
Ca�acitance (�n�ut��ut�ut)
�n�ut Ca�acitance
�ut�ut �i�e �ime (�0�90%)
�ut�ut �all �ime (90��0%)
Single Channel Product Only
�ut�ut Enable �ime to �ogic ��igh
�ut�ut Enable �ime to �ogic �ow
�ut�ut Di�able �ime �rom �ogic ��igh
�ut�ut Di�able �ime �rom �ogic �ow
Multi-Channel Product Only
�n�ut��n�ut �n�ulation �eakage
Current
�e�i�tance (�n�ut��n�ut)
Ca�acitance (�n�ut��n�ut)
minal� �horted together.
�). CM
�.0 �).
out�ut �ul�e. �he t
trailing edge o� the out�ut �ul�e.
(Subgrou�� � and 9�� � and �0�� � and ���� re��ectivel��).
fied �or all lot� not ��ecificall�� te�ted.
P���
�
�ro�agation dela�� i� mea�ured �rom the �0% �oint on the leading edge o� the in�ut �ul�e to the �.� � �oint on the leading edge o� the
i� the ma�imum rate o� ri�e o� the common mode voltage that can be �u�tained with the out�ut voltage in the logic low �tate (�
��
i� the ma�imum rate o� �all o� the common mode voltage that can be �u�tained with the out�ut voltage in the logic high �tate (�
P���
�ro�agation dela�� i� mea�ured �rom the �0% �oint on the trailing edge o� the in�ut �ul�e to the �.� � �oint on the
�
= ���C�� �
CC
= � ��� �
Symbol
t
t
�
D�
�
C
t
t
D�
C
�
C
��YS
PZ��
P��Z
P�Z
PZ�
�
t
t
���
���
���
�N
���
���
r
�
�(�N)
�
�
= � m� unle�� otherwi�e ��ecified.
�
�
�
���
Test Conditions
�
= 0 ��� � = � M��z
= �00 ��� t = � �
���
�
��� ≤ 6�%��
� = � M��z
� = � M��z
�
�
�
���
= �00 �dc
CC
= � m�
= �00 �
= � �
��.��
�0
�0
0.07
Typ.
�.0
0.�
�.�
�0
���
�0
�0
�0
���
��
��
��
m���C
Units
m�
n�
��
��
��
n�
n�
n�
n�
n�
n�
W
W
Fig.
��� 7
��� 7
�
�
�
�
�
Notes
��� �0
��� �
��� �
�
< 0.�
�
�
�
�
9
9
9
�
��