HCPL-5500#100 Avago Technologies US Inc., HCPL-5500#100 Datasheet - Page 12
![ISOLAT 1.5KVDC 1CH OPEN 8SMD BJ](/photos/26/81/268190/93472_sml.jpg)
HCPL-5500#100
Manufacturer Part Number
HCPL-5500#100
Description
ISOLAT 1.5KVDC 1CH OPEN 8SMD BJ
Manufacturer
Avago Technologies US Inc.
Datasheet
1.HCPL-5500.pdf
(13 pages)
Specifications of HCPL-5500#100
Input Type
DC
Package / Case
8-SMD Butt Joint
Voltage - Isolation
1500VDC
Number Of Channels
1, Unidirectional
Current - Output / Channel
8mA
Data Rate
400kbps
Propagation Delay High - Low @ If
400ns @ 16mA
Current - Dc Forward (if)
20mA
Output Type
Open Collector
Mounting Type
Surface Mount
Output Device
Phototransistor
Configuration
1 Channel
Current Transfer Ratio
20 %
Maximum Baud Rate
400 KBps
Maximum Forward Diode Voltage
1.9 V
Maximum Input Diode Current
20 mA
Maximum Power Dissipation
200 mW
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 55 C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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R
Figure 10. Test Circuit for Transient Immunity and Typical Waveforms.
TTL
Figure 11. Recommended Logic Interface.
Figure 12. Operating Circuit for Burn-In and Steady State Life Tests. All
Channels Tested Simultaneously.
1
M
NOTE: BASE LEAD NOT CONNECTED.
NOMINAL CONDITIONS
PER CHANNEL: I
T
A
NOTE: BASE LEAD NOT CONNECTED.
220 Ω
= +125 ˚C
V
V
IN
FF
+
I
F
(EACH INPUT)
5 V
-
I
I
F
O
CC
B
A
EACH CHANNEL
= 20 mA
= 4 mA
COMMON V
= 30 µA
SINGLE CHANNEL OR
D.U.T.
PULSE GEN.
+
D.U.T.
GND
V
V
CC
CC
CM
DEVICES
GND
V
-
CC
D.U.T.*
0.01 µF
V
CC
GND
V
CC
LOGIC GATE
V
O
R
L
R
(EACH OUTPUT)
L
V
0.1 µF
CC
+5 V
V
O
V
OC
*The equivalent output load resistance is affected by the LSTTL input
Logic Family
Device No.
V
R
CC
L
current and is approximately 8.2 kΩ. This is a worst case design
which takes into account 25% degradation of CTR. See App. Note
1002 to assess actual degradation and lifetime.
5% Tolerance
18 kW *
54LS14
LSTTL
5 V
8. kW
5 V
CD40106BM
CMOS
kW
15 V