HCPL-0723-560E Avago Technologies US Inc., HCPL-0723-560E Datasheet - Page 10
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HCPL-0723-560E
Manufacturer Part Number
HCPL-0723-560E
Description
OPTOCOUPLER 50MBD 2NS VDE 8-SOIC
Manufacturer
Avago Technologies US Inc.
Datasheet
1.HCPL-7723-300.pdf
(12 pages)
Specifications of HCPL-0723-560E
Package / Case
8-SOIC (0.154", 3.90mm Width)
Voltage - Isolation
3750Vrms
Number Of Channels
1, Unidirectional
Current - Output / Channel
10mA
Data Rate
50MBd
Propagation Delay High - Low @ If
16ns
Input Type
Logic
Output Type
Push-Pull, Totem-Pole
Mounting Type
Surface Mount
Isolation Voltage
3750 Vrms
Maximum Continuous Output Current
10 mA
Maximum Fall Time
6 ns
Maximum Rise Time
8 ns
Output Device
Logic Gate Photo IC
Configuration
1 Channel
Maximum Baud Rate
50 MBps
Maximum Power Dissipation
150 mW
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Elements
1
Baud Rate
50Mbps
Output Current
10mA
Package Type
SOIC
Operating Temp Range
-40C to 85C
Power Dissipation
150mW
Propagation Delay Time
22ns
Pin Count
8
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HCPL-0723-560E
Manufacturer:
OMRON
Quantity:
2 000
Application Information
Bypassing and PC Board Layout
The HCPL-7723/0723 optocouplers are extremely easy to
use. No external interface circuitry is required because
the HCPL-7723/0723 use high-speed CMOS IC technol-
ogy allowing CMOS logic to be connected directly to the
inputs and outputs.
As shown in Figure 1, the only external components
required for proper operation are two bypass capacitors.
Capacitor values should be between 0.01 µF and 0.1 µF.
For each capacitor, the total lead length between both
ends of the capacitor and the power-supply pins should
not exceed 20 mm. Figure 2 illustrates the recommended
printed circuit board layout for the HCPL-7723/0723.
Figure 1. Functional diagram.
Figure 2. Recommended printed circuit board layout.
Figure 3. Timing diagram to illustrate propagation delay, tplh and tphl.
10
V
GND
V
INPUT
OUTPUT
DD1
DD1
V
V
I
1
I
V
V
O
I
GND
C1
1
10%
NC
C1, C2 = 0.01 µF TO 0.1 µF
C1
1
2
3
4
90%
t
PLH
t
PHL
8
7
6
5
NC
90%
GND
50%
C2
10%
2
V
V
DD2
O
5 V CMOS
0 V
V
2.5 V CMOS
V
OH
OL
Propagation Delay, Pulse-Width Distortion and Propa-
gation Delay Skew
Propagation Delay is a figure of merit which describes
how quickly a logic signal propagates through a system
as illustrated in Figure 3. The propagation delay from low
to high (t
signal to propagate to the output, causing the output to
change from low to high. Similarly, the propagation delay
from high to low (t
the input signal to propagate to the output, causing the
output to change from high to low.
C2
PLH
C1, C2 = 0.01 µF TO 0.1 µF
) is the amount of time required for an input
PHL
) is the amount of time required for
V
V
GND
DD2
O
2