HCPL-0710#500 Avago Technologies US Inc., HCPL-0710#500 Datasheet - Page 14
![OPTOCOUPLER CMOS 12MBD 8-SOIC](/photos/7/65/76546/516-8-soic_sml.jpg)
HCPL-0710#500
Manufacturer Part Number
HCPL-0710#500
Description
OPTOCOUPLER CMOS 12MBD 8-SOIC
Manufacturer
Avago Technologies US Inc.
Datasheet
1.HCPL-7710-000E.pdf
(18 pages)
Specifications of HCPL-0710#500
Voltage - Isolation
3750Vrms
Number Of Channels
1, Unidirectional
Current - Output / Channel
10mA
Data Rate
12.5MBd
Propagation Delay High - Low @ If
20ns
Input Type
Logic
Output Type
Push-Pull, Totem-Pole
Mounting Type
Surface Mount
Package / Case
8-SOIC (0.154", 3.90mm Width)
No. Of Channels
1
Isolation Voltage
3.75kV
Optocoupler Output Type
Gate Drive
Input Current
10µA
Output Voltage
5V
Opto Case Style
SOIC
No. Of Pins
8
Propagation Delay Low-high
40ns
Common Mode Voltage Vcm
1000V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
516-1116-2
Available stocks
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Part Number
Manufacturer
Quantity
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14
Isolated Node with Transceiver Powered by the Network
Figure 20 shows a node powered by both the network
and another source. In this case, the transceiver and
isolated (network) side of the two optocouplers are
powered by the network. The rest of the node is
powered by the AC line which is very beneficial when
an application requires a significant amount of power.
This method is also desirable as it does not heavily load
the network.
More importantly, the unique “dual-inverting” design
of the HCPL-x710 ensure the network will not “lock-up”
if either AC line power to the node is lost or the node
powered-off. Specifically, when input power (V
the HCPL-x710 located in the transmit path is eliminat-
ed, a RECESSIVE bus state is ensured as the HCPL-x710
output voltage (V
Figure 20. Isolated node with transceiver powered by the network.
DRAIN/SHIELD
SIGNAL
POWER
NETWORK
SUPPLY
POWER
O
) go HIGH.
NODE/APP SPECIFIC
HCPL
0710
TRANSCEIVER
* OPTIONAL FOR BUS V + SENSE
uP/CAN
HCPL-0710 fig 19
HCPL
0710
DD1
NON ISO
HCPL
REG.
0710
5 V
) to
AC LINE
V+ (SIGNAL)
V– (SIGNAL)
V+ (POWER)
V– (POWER)
*Bus V+ Sensing
It is suggested that the Bus V+ sense block shown in
Figure 20 be implemented. A locally powered node with
an un-powered isolated Physical Layer will accumulate
errors and become bus-off if it attempts to transmit. The
Bus V+ sense signal would be used to change the BOI
attribute of the DeviceNet Object to the “auto-reset”
(01) value. Refer to Volume 1, Section 5.5.3. This would
cause the node to continually reset until bus power was
detected. Once power was detected, the BOI attribute
would be returned to the “hold in bus-off” (00) value.
The BOI attribute should not be left in the “auto-reset”
(01) value since this defeats the jabber protection ca-
pability of the CAN error confinement. Any inexpensive
low frequency optical isolator can be used to implement
this feature.
GALVANIC
ISOLATION
BOUNDARY