ACPL-3130-000E Avago Technologies US Inc., ACPL-3130-000E Datasheet - Page 19

• Manufacturer Part Number: ACPL-3130-000E
• Description: OPTOCOUPLER IGBT 2.5A 8-DIP
• Manufacturer: Avago Technologies US Inc.

Specifications of ACPL-3130-000E

• Voltage - Isolation: 3750Vrms
• Number Of Channels: 1, Unidirectional
• Current - Output / Channel: 2.5A
• Propagation Delay High - Low @ If: 300ns @ 7mA ~ 16mA
• Current - Dc Forward (if): 25mA
• Input Type: DC
• Output Type: Push-Pull, Totem-Pole
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• No. Of Channels: 1
• Optocoupler Output Type: Gate Drive
• Input Current: 16mA
• Output Voltage: 30V
• Opto Case Style: DIP
• No. Of Pins: 8
• Input Current Max: 5mA
• Isolation Voltage: 3.75kV
• Propagation Delay: 0.5µs
• Rohs Compliant: Yes
• Common Mode Ratio: 40
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 37. Recommended LED Drive Circuit for Ultra-High CMR.
Under Voltage Lockout Feature. (Discussion applies to
ACPL-3130, ACPL-J313, and ACNW3130)
The ACPL-3130 contains an under voltage lockout (UVLO)
feature that is designed to protect the IGBT under fault
conditions which cause the ACPL-3130 supply voltage
(equivalent to the fully-charged IGBT gate voltage) to
drop below a level necessary to keep the IGBT in a low
resistance state. When the ACPL-3130 output is in the high
state and the supply voltage drops below the ACPL-3130
V
output will go into the low state with a typical delay, UVLO
Turn Off Delay, of 0.6 µs.
When the ACPL-3130 output is in the low state and the
supply voltage rises above the ACPL-3130 V
(11.0 < V
the high state (assumes LED is “ON”) with a typical delay,
UVLO Turn On Delay of 0.8 µs.
Figure 38. Under Voltage Lock Out.

UVLO
+5 V
14
12
10
8
6
4
2
0
0
– threshold (9.5 < V
(V
UVLO
CC
1
2
3
4
- V
(10.7, 0.1)
5
(10.7, 9.2)
+ < 13.5) the optocoupler output will go into
EE
C
C
) - SUPPLY VOLTAGE - V
LEDP
LEDN
SHIELD
10
(12.3, 0.1)
(12.3, 10.8)
UVLO
15
– < 12.0) the optocoupler
20
8
7
6
5
UVLO
+ threshold
Dead Time and Propagation Delay Specifications. (Discus-
sion applies to ACPL-3130, ACPL-J313, and ACNW3130)
The ACPL-3130 includes a Propagation Delay Difference
(PDD) specification intended to help designers minimize
“dead time” in their power inverter designs. Dead time
is the time period during which both the high and low
side power transistors (Q1 and Q2 in Figure 29) are off.
Any overlap in Q1 and Q2 conduction will result in large
currents flowing through the power devices between the
high and low voltage motor rails.
Figure 39. Minimum LED Skew for Zero Dead Time.
To minimize dead time in a given design, the turn on of
LED2 should be delayed (relative to the turn off of LED1)
so that under worst-case conditions, transistor Q1 has just
turned off when transistor Q2 turns on, as shown in Figure
35. T he amount of delay necessary to achieve this condition
is equal to the maximum value of the propagation delay
difference specification, PDD
350 ns over the operating temperature range of -40°C to
100°C.
Delaying the LED signal by the maximum propagation
delay difference ensures that the minimum dead time is
zero, but it does not tell a designer what the maximum
dead time will be. The maximum dead time is equivalent
to the difference between the maximum and minimum
propagation delay difference specifications as shown in
Figure 40. The maximum dead time for the ACPL-3130 is
700 ns (= 350 ns - (-350 ns)) over an operating temperature
range of - 40°C to 100°C.
Note that the propagation delays used to calculate PDD
and dead time are taken at equal temperatures and test
conditions since the optocouplers under consideration
are typically mounted in close proximity to each other and
are switching identical IGBTs.
V
V
I
I
OUT1
OUT2
LED1
LED2
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
PDD* MAX = (t
t
PHL MAX
Q2 OFF
Q1 ON
PHL
t
MAX
PLH MIN
- t
, which is specified to be
PLH
)
MAX
= t
PHL MAX
Q1 OFF
Q2 ON
- t
PLH MIN