ACPL-072L-000E Avago Technologies US Inc., ACPL-072L-000E Datasheet - Page 10

• Manufacturer Part Number: ACPL-072L-000E
• Description: OPTOCOUPLER 3.3/5V 25MBD 8-SOIC
• Manufacturer: Avago Technologies US Inc.

Specifications of ACPL-072L-000E

• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Voltage - Isolation: 3750Vrms
• Number Of Channels: 1, Unidirectional
• Current - Output / Channel: 10mA
• Data Rate: 25MBd
• Propagation Delay High - Low @ If: 23.5ns
• Input Type: Logic
• Output Type: Push-Pull, Totem-Pole
• Mounting Type: Surface Mount
• Isolation Voltage: 3750 Vrms
• Maximum Fall Time: 8 ns
• Maximum Rise Time: 9 ns
• Output Device: Logic Gate Photo IC
• Configuration: 1 Channel
• Maximum Baud Rate: 25 MBd
• Maximum Power Dissipation: 150 mW
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 516-1732-5; ACPL-072L-000E

Application Information
Bypassing and PC Board Layout
The ACPL-x72L optocouplers are extremely easy to use.
No external interface circuitry is required because ACPL-
x72L uses high speed CMOS IC technology allowing
CMOS logic to be connected directly to the inputs and
outputs.
As shown in Figure 7, the only external components
required for proper operation are two bypass capacitors.
Capacitor values should be between 0.01mF and 0.1mF.
For each capacitor, the total lead length between both
ends of the capacitor and power supply pins should not
exceed 20mm. Figure 8 illustrates the recommended
printed circuit board layout for ACPL-x72L.
Figure 7. Recommended Circuit Diagram
Figure 8. Recommended Printed Circuit Board Layout
10
V
V
GND
DD1
DD1
V
V
1
I
I
GND
C1
1
NC
C1
1
2
3
4
C1, C2 = 0.01 µF TO 0.1 µF
8
7
6
5
NC
GND
C2
2
V
V
DD2
O
C2
Propagation Delay, Pulse-Width Distortion and Propa-
gation Delay Skew
Propagation Delay is a figure of merit which describes
how quickly a logic signal propagates through a system.
The propagation delay from a low to high (t
amount of time required for an input signal to propagate
to the output, causing the output to change from low to
high. Similarly, the propagation delay from high to low
(t
to propagate to the output, causing the output to change
from high to low. Please see Figure 9.
Figure 9. Signal plot shows how propagation delay is defined
Pulse-width distortion (PWD) is the difference between
t
rate capability of a transmission system. PWD can be
expressed in percent by dividing the PWD (in ns) by the
minimum pulse width (in ns) being transmitted. Typically,
PWD on the order of 20-30% of the minimum pulse
width is tolerable. The PWD specification for ACPL-x72L
is 6ns (15%) maximum across recommended operating
conditions.
INPUT
OUTPUT
PHL
PHL
C1, C2 = 0.01 µF TO 0.1 µF
V
) is the amount of time required for the input signal
and t
V
O
I
PLH
10%
and often determines the maximum data
V
V O
GND
90%
DD2
t
PLH
2
t
PHL
90%
50%
10%
PLH
5 V CMOS
0 V
V
2.5 V CMOS
V
OH
OL
) is the