SI8452BB-B-IS1 Silicon Laboratories Inc, SI8452BB-B-IS1 Datasheet - Page 18

IC ISOLATOR 5CH 5.5V 16-SOIC

SI8452BB-B-IS1

Manufacturer Part Number
SI8452BB-B-IS1
Description
IC ISOLATOR 5CH 5.5V 16-SOIC
Manufacturer
Silicon Laboratories Inc
Series
ISOpror
Datasheets

Specifications of SI8452BB-B-IS1

Number Of Channels
5
Package / Case
16-SOIC (3.9mm Width)
Inputs - Side 1/side 2
3/2
Isolation Rating
2500Vrms
Voltage - Supply
2.7 V ~ 5.5 V
Data Rate
150Mbps
Propagation Delay
6ns
Output Type
Tri-State
Operating Temperature
-40°C ~ 125°C
Mounting Style
SMD/SMT
Propagation Delay Time
6 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Supply Current
6 mA
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Operating Temperature (max)
125C
Operating Temperature (min)
-40C
Pin Count
16
Mounting
Surface Mount
Package Type
SOIC N
Case Length
9.9mm
Case Height
1.5(Max)mm
Screening Level
Automotive
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI8452BB-B-IS1
Manufacturer:
Silicon Labs
Quantity:
135
Si8450/51/52/55
18
Notes:
Input
V
1. VDDI and VDDO are the input and output power supplies. V
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si845x is
4. No Connect (NC) replaces EN1 on Si8450. No Connects are not internally connected and can be left floating, tied to
5. "Powered" state (P) is defined as 2.70 V < VDD < 5.5 V.
6. "Unpowered" state (UP) is defined as VDD = 0 V.
7. When using the enable pin (EN) function, the output pin state is driven to a logic low state when the EN pin is disabled
H
X
X
X
X
L
I
1,2
is the enable control input located on the same output side.
operating in noisy environments.
VDD, or tied to GND.
(EN = 0) in Revision A. Revision B outputs go into a high-impedance state when the EN pin is disabled (EN = 0). See
"4. Errata and Design Migration Guidelines (Revision A Only)" on page 26 for more details.
Input
H or NC
H or NC
H or NC
EN
X
L
L
1,2,3,4
State
VDDI
UP
UP
P
P
P
P
1,5,6
Table 12. Si845x Logic Operation Table
State
VDDO
UP
P
P
P
P
P
1,5,6
Undetermined Upon transition of VDDO from unpowered to pow-
V
O
Hi-Z or L
Hi-Z or L
Output
Rev. 1.2
H
L
L
7
7
1,2
I
and V
Disabled.
ered, V
than 1 µs.
Disabled.
ered, V
1 µs, if EN is in either the H or NC state. Upon tran-
sition of VDDO from unpowered to powered, V
returns to Hi-Z within 1 µs if EN is L.
Enabled, normal operation.
Upon transition of VDDI from unpowered to pow-
O
are the respective input and output terminals. EN
O
O
returns to the same state as V
returns to the same state as V
Comments
I
I
in less
within
O

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