HCPL-0930-500 Avago Technologies US Inc., HCPL-0930-500 Datasheet - Page 9
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HCPL-0930-500
Manufacturer Part Number
HCPL-0930-500
Description
ISOLATOR DGTL 2CH 100MBD 8-SOIC
Manufacturer
Avago Technologies US Inc.
Datasheet
1.HCPL-0900-000E.pdf
(14 pages)
Specifications of HCPL-0930-500
Inputs - Side 1/side 2
2/0
Number Of Channels
2
Isolation Rating
2500Vrms
Voltage - Supply
3 V ~ 5.5 V
Data Rate
100MBd
Propagation Delay
12ns
Output Type
CMOS
Package / Case
8-SOIC (3.9mm Width)
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HCPL-0930-500
Manufacturer:
LSI
Quantity:
3 033
3.3V operation: Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at T
Parameter
Quiescent Supply Current 1
HCPL-9000/-0900
HCPL-9030/-0930
HCPL-9031/-0931
HCPL-900J/-090J
HCPL-901J/-091J
HCPL-902J/-092J
Quiescent Supply Current 2
HCPL-9000/-0900
HCPL-9030/-0930
HCPL-9031/-0931
HCPL-900J/-090J
HCPL-901J/-091J
HCPL-902J/-092J
Logic Input Current
Logic High Output Voltage
Logic Low Output Voltage
Switching Specifications
Maximum Data Rate
Clock Frequency
Propagation Delay Time to Logic
Propagation Delay Time toLogic
Pulse Width
Pulse Width Distortion
Propagation Delay Skew
Output Rise Time (10 – 90%)
Output Fall Time (10 – 90%)
Propagation Delay Enable to Output (Single Channel)
Channel-to-Channel Skew
Common Mode Transient Immunity
Notes:
1. PWD is defined as |t
2. t
3. CM
input voltage that can be sustained while maintaining V
voltage edges.
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Avago recommends that all integrated circuits
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to
complete failure.
9
|t
(Dual and Quad Channels)
(Output Logic High or Logic Low)
Low Output
High Output
PSK
PHL
High to High Impedance
Low to High Impedance
High Impedance to High
High Impedance to Low
H
is equal to the magnitude of the worst case difference in t
– t
is the maximum common mode voltage slew rate that can be sustained while maintaining V
PLH
|
PHL
-t
PLH
[1]
|. %PWD is equal to the PWD divided by the pulse width.
[2]
A
=+25°C, V
[3]
Symbol
I
I
I
V
V
fmax
t
t
t
|PWD|
t
t
t
t
t
t
t
t
|CM
|CM
DD1
DD2
IN
PHL
PLH
PW
PSK
R
F
PHZ
PLZ
PZH
PZL
CSK
OH
OL
DD1
H
L
|
|
= V
OUT
DD2
< 0.8V. The common mode voltage slew rates apply to both rising and falling common mode
= +3.3 V.
PHL
V
0.8*V
DD2
Min.
and/or t
100
10
15
-10
– 0.1
DD2
PLH
that will be seen between units at 25°C.
V
0.008
0.008
0.018
DD2
Typ.
110
1.5
3.3
1.5
3.3
3.3
1.5
5.5
3.3
3.0
0.5
12
12
18
2
4
2
2
3
3
3
3
2
V
0
– 0.5
DD2
OUT
> 0.8V
Max.
0.01
0.01
0.02
2.0
4.0
2.0
4.0
4.0
2.0
8.0
4.0
6.0
0.1
10
0.8
50
18
18
3
6
4
4
5
5
5
5
3
DD2
. CM
L
is the maximum common mode
Units Test Conditions
mA
mA
μA
V
V
V
V
MBd
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
kV/μs V
V
V
I
I
I
I
C
OUT
OUT
OUT
OUT
IN
IN
cm
L
= 15 pF
= 0V
= 0V
= -20 μA, V
= -4 mA, V
= 20 μA, V
= 4 mA, V
= 1000V
IN
IN
IN
IN
= V
= V
= V
= V
IL
IH
IL
IH