ADUM3300BRWZ Analog Devices Inc, ADUM3300BRWZ Datasheet - Page 9

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ADUM3300BRWZ

Manufacturer Part Number
ADUM3300BRWZ
Description
IC DIGITAL ISOLATOR 3CH 16-SOIC
Manufacturer
Analog Devices Inc
Series
iCoupler®r
Datasheet

Specifications of ADUM3300BRWZ

Propagation Delay
32ns
Inputs - Side 1/side 2
3/0
Number Of Channels
3
Isolation Rating
2500Vrms
Voltage - Supply
2.7 V ~ 5.5 V
Data Rate
10Mbps
Output Type
Logic
Package / Case
16-SOIC (0.300", 7.5mm Width)
Operating Temperature
-40°C ~ 105°C
No. Of Channels
3
Supply Current
7mA
Supply Voltage Range
2.7V To 5.5V
Digital Ic Case Style
SOIC
No. Of Pins
16
Operating Temperature Range
-40°C To +105°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Parameter
1
2
3
4
5
6
7
8
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
t
measured from the 50% level of the rising edge of the V
t
within the recommended operating conditions.
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
CM
that can be sustained while maintaining V
magnitude is the range over which the common mode is slewed.
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through
Figure 12 for total V
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
PHL
PSK
For All Models
H
is the magnitude of the worst-case difference in t
propagation delay is measured from the 50% level of the falling edge of the V
Output Disable Propagation Delay
Output Enable Propagation Delay
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
Common-Mode Transient Immunity
Refresh Rate
Input Dynamic Supply Current per Channel
Output Dynamic Supply Current per Channel
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
at Logic High Output
(High Impedance-to-High/Low)
at Logic Low Output
(High/Low-to-High Impedance)
5 V/3 V Operation
3 V/5 V Operation
5 V/3 V Operation
3 V/5 V Operation
5 V/3 V Operation
3 V/5 V Operation
5 V/3 V Operation
3 V/5 V Operation
DD1
and V
DD2
7
supply currents as a function of data rate for ADuM3300/ADuM3301/ADuM3302 channel configurations.
7
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
8
PHL
8
or t
Ix
signal to the 50% level of the rising edge of the V
PLH
Symbol
t
t
t
|CM
|CM
f
I
I
that is measured between units at the same operating temperature, supply voltages, and output load
r
DDI (D)
DDO (D)
PHZ
PZH
R
/t
f
, t
, t
H
L
|
|
PLH
PZL
Rev. A | Page 9 of 20
Min
25
25
Ix
signal to the 50% level of the falling edge of the V
Typ
6
6
3.0
2.5
35
35
1.2
1.1
0.20
0.10
0.05
0.03
O
> 0.8 V
Max Unit
8
8
DD2
Ox
. CM
signal.
L
mA/Mbps
mA/Mbps
mA/Mbps
mA/Mbps
ns
ns
ns
ns
kV/μs
kV/μs
Mbps
Mbps
is the maximum common-mode voltage slew rate
ADuM3300/ADuM3301
Test Conditions
C
C
C
V
transient magnitude = 800 V
V
transient magnitude = 800 V
L
L
L
Ix
Ix
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= V
= 0 V, V
Ox
signal. t
DD1
or V
CM
PLH
= 1000 V,
DD2
propagation delay is
, V
CM
= 1000 V,

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