HCPL-090J-000E Avago Technologies US Inc., HCPL-090J-000E Datasheet - Page 13
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HCPL-090J-000E
Manufacturer Part Number
HCPL-090J-000E
Description
ISOLATOR DGTL 4CH 100MBD 16-SOIC
Manufacturer
Avago Technologies US Inc.
Datasheet
1.HCPL-0900-000E.pdf
(14 pages)
Specifications of HCPL-090J-000E
Package / Case
16-SOIC (3.9mm Width)
Inputs - Side 1/side 2
4/0
Number Of Channels
4
Isolation Rating
2500Vrms
Voltage - Supply
3 V ~ 5.5 V
Data Rate
100MBd
Propagation Delay
12ns
Output Type
CMOS
Operating Temperature
-40°C ~ 100°C
Mounting Style
SMD/SMT
No. Of Channels
4
Isolation Voltage
2.5kV
Optocoupler Output Type
Logic Gate
Input Current
10µA
Output Voltage
5V
Opto Case Style
SOIC
No. Of Pins
16
Data Rate Max
100Mbps
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
516-1875-5
HCPL-090J-000E
HCPL-090J-000E
Propagation Delay, Pulse Width Distortion and Propaga-
tion Delay Skew
Propagation Delay is a figure of merit, which describes
how quickly a logic signal propagates through a system
as illustrated in Figure 3.
INPUT
Figure 3. Timing Diagrams to Illustrate Propagation Delay, t
The propagation delay from low to high, t
amount of time required for an input signal to propagate
to the output, causing the output to change from low to
high. Similarly, the propagation delay from high to low,
t
propagate to the output, causing the output to change
from high to low.
Pulse Width Distortion, PWD, is the difference between t
and t
pability of a transmission system. PWD can be expressed in
percent by dividing the PWD (in ns) by the minimum pulse
width (in ns) being transmitted. Typically, PWD on the order
of 20 – 30% of the minimum pulse width is tolerable.
Propagation Delay Skew, t
Skew, t
data transmission applications where synchronization of
signals on parallel data lines is a concern. If the parallel
data is being sent through channels of the digital
isolators, differences in propagation delays will cause
the data to arrive at the outputs of the digital isolators
at different times. If this difference in propagation delay
is large enough, it will limit the maximum transmission
rate at which parallel data can be sent through the digital
isolators.
t
maximum propagation delays, either t
or more devices which are operating under the same con-
ditions (i.e., the same drive current, supply voltage, output
load, and operating temperature). t
difference between the minimum and maximum propaga-
tion delays, either t
within a single device (applicable to dual and quad channel
devices) which are operating under the same conditions.
13
OUTPUT
PHL
PSK
V
, is the amount of time required for the input signal to
is defined as the difference between the minimum and
OUT
V
IN
PLH
CSK
and often determines the maximum data rate ca-
, are critical parameters to consider in parallel
10%
90%
PLH
t PLH
or t
PHL
, among two or more channels
PSK
, and Channel-to-Channel
t PHL
90%
PLH
CSK
or t
is defined as the
50%
PHL
10%
, among two
PLH
PLH
and t
5 V CMOS
2.5 V CMOS
, is the
0 V
V OH
V OL
PHL
.
PHL
As illustrated in Figure 4, if the inputs of two or more
devices are switched either ON or OFF at the same time,
t
delay, either t
delay, either t
Figure 4. Timing Diagrams to Illustrate Propagation Delay Skew.
As mentioned earlier, t
parallel data transmission rate. Figure 5 shows the timing
diagram of a typical parallel data transmission application
with both the clock and data lines being sent through the
digital isolators. The figure shows data and clock signals at
the inputs and outputs of the digital isolators. In this case,
the data is clocked off the rising edge of the clock.
Figure 5. Parallel Data Transmission.
PSK
is the difference between the minimum propagation
V
V
OUTPUTS
V
OUT
OUT
INPUTS
V
IN
IN
CLOCK
CLOCK
DATA
DATA
PLH
PLH
or t
or t
50%
50%
t
PSK
CMOS
2.5 V
PHL
PHL
.
t
, and the maximum propagation
PSK
PSK
, can determine the maximum
t
PSK
2.5 V
CMOS