ADUM1410BRWZ Analog Devices Inc, ADUM1410BRWZ Datasheet - Page 9

• Manufacturer Part Number: ADUM1410BRWZ
• Description: IC ISOLATOR DGTL 4CH UNI 16-SOIC
• Manufacturer: Analog Devices Inc
• Series: iCoupler®r

Specifications of ADUM1410BRWZ

• Propagation Delay: 30ns
• Inputs - Side 1/side 2: 4/0
• Number Of Channels: 4
• Isolation Rating: 2500Vrms
• Voltage - Supply: 2.7 V ~ 5.5 V
• Data Rate: 10Mbps
• Output Type: Logic
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Operating Temperature: -40°C ~ 105°C
• No. Of Channels: 4
• Supply Current: 8.8mA
• Supply Voltage Range: 2.7V To 5.5V
• Digital Ic Case Style: SOIC
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +105°C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 105C
• Package Type: SOIC W
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Parameter
1
2
3
4
5
6
7
8
9
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
t
measured from the 50% level of the rising edge of the V
t
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
|CM
that can be sustained while maintaining V
magnitude is the range over which the common mode is slewed.
Input enable time is the duration from when V
transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the
much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when V
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the P
See Figure through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure
Figure 15
within the recommended operating conditions.
on per-channel supply current for unloaded and loaded conditions. See the
for a given data rate.
PHL
PSK
All Models
is the magnitude of the worst-case difference in t
propagation delay is measured from the 50% level of the falling edge of the V
H
Channel-to-Channel Matching,
Channel-to-Channel Matching,
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient
Common-Mode Transient
Refresh Rate
Input Dynamic Supply Current
Output Dynamic Supply Current
Input Enable Time
Input Disable Time
| is the maximum common-mode voltage slew rate that can be sustained while maintaining V
Opposing-Directional Channels
Immunity at Logic High Output
Codirectional Channels
Immunity at Logic Low Output
5 V/3 V Operation
3 V/5 V Operation
5 V/3 V Operation
3 V/5 V Operation
5 V Operation
3 V Operation
5 V Operation
3 V Operation
per Channel
per Channel
for total V
8
DD1
9
9
and V
8
8
DD2
supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations.
6
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
6
7
7
DISABLE
Symbol
t
t
t
|CM
|CM
f
t
t
I
I
DDI (D)
DDO (D)
r
PSKCD
PSKOD
R
ENABLE
DISABLE
/t
is set low until the output states are guaranteed to match the input states in the absence of any input data logic
F
PHL
H
L
|
|
or t
Ix
signal to the 50% level of the rising edge of the V
PLH
that is measured between units at the same operating temperature, supply voltages, and output load
Min
25
25
Rev. H | Page 9 of 24
Power Consumption
Ix
signal to the 50% level of the falling edge of the V
Typ
2.5
2.5
35
35
1.2
1.1
2.0
5.0
0.12
0.07
0.04
0.02
section for guidance on calculating the per-channel supply current
O
> 0.8 V
ADuM1410/ADuM1411/ADuM1412
Ox
DD2
2
signal.
logic state (see Table 14).
. |CM
Max Unit
5
6
L
| is the maximum common-mode voltage slew rate
ns
ns
ns
ns
kV/μs
kV/μs
Mbps
Mbps
μs
μs
mA/
Mbps
mA/
Mbps
mA/
Mbps
mA/
Mbps
Figure 8
Test Conditions
C
C
C
V
transient magnitude = 800 V
V
magnitude = 800 V
V
V
L
L
L
Ix
Ix
IA
IA
through
Ox
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
, V
, V
= V
= 0 V, V
signal. t
ower Consumption
IB
IB
DD1
, V
, V
IC
IC
Figure 10
or V
, V
, V
CM
PLH
ID
ID
= 1000 V, transient
propagation delay is
DD2
= 0 V or V
= 0 V or V
DISABLE
, V
for information
11
CM
is set high
through
= 1000 V,
section.
DD1
DD1