CS2082EDWR20 ON Semiconductor, CS2082EDWR20 Datasheet - Page 8

• Manufacturer Part Number: CS2082EDWR20
• Description: IC DRIVR ASIC DUAL AIRBAG 20SOIC
• Manufacturer: ON Semiconductor

Specifications of CS2082EDWR20

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: CS2082EDWR20OS

squib resistance) may be reported by the fault register and
should be ignored.
calculated as:
where V
I
typical value for P is 300 mW when V
V
corresponding increase in die temperature which will cause
a corresponding decrease in time to thermal shutdown of the
CS2082. To minimize the impact of squib resistive
measurements on time to thermal shutdown a 5% duty cycle
is recommended.
Analog MUX – $4d
pin. The states are: High–Z; MR voltage; A
proportion of V
Analog Mux select register bit definitions are shown in
Table 6. All other states will be interpreted as High–Z. At
power–up, the default state is ‘High–Z.’
Low Side Switch Control – $5d
a data bit is low that switch is turned on. More than one
switch can be activated at a time. Bit assignment is shown in
Table 7. At power–up, no switches are active.
SQUIB
DIFF
Power Dissipation during resistive measurement can be
The resultant increase in power dissipation will cause a
The $4d command selects one of five states at the A
The $5d command activates the low side switches. When
D3
0
0
0
0
1
P + I SQUIB (V BAT * V DIFF ) * (I SQUIB
= 50 mV, R
is the measurement current through the squib. A
BAT
Table 6. Analog MUX Output Select
D2
0
0
0
1
0
is the voltage at the CS2082 V
BAT
SQUIB
D1
; proportion of V
0
0
1
0
0
= 2.0
D0
0
1
0
0
0
and R
High–Z
MR
AIN
BAT
RES
RES
BAT
MR
. The active–high
State
= 13.5,
= 49.9 .
BAT
IN
R MR)
voltage;
pin and
http://onsemi.com
OUT
CS2082
8
Auxiliary Control Register – $6d
threshold. The threshold determines when the $1x Status
Register reports V
8. At power–up, default trip is 17 V.
High Side Switch Control – $Ad
a data bit is high, that switch is turned on. More than one
switch can be activated at a time. Bit assignment is shown in
Table 9. Note that the $5d and $Ad commands are binary
complements, i.e., by sending 1010xx11, both high side
switches are activated, and by sending the complement
0101xx00, both low side switches are activated. At
power–up, no switches are active.
The $6d command selects the V
The $Ad command activates the high side switches. When
D3
D3
D3
x
x
x
x
x
x
x
x
x
x
D2
D2
D2
Table 8. V
x
x
x
x
x
x
x
x
x
x
Table 9. High Side Switch Select
Table 7. Low Side Switch Select
RES
D1
D1
D1
0
0
1
1
x
x
0
0
1
1
RES
= 1. Bit assignment is shown in Table
Monitor Trip Select
D0
D0
D0
0
1
0
1
0
1
0
1
0
1
BOTH
SL2
SL1
NONE
17 V
23 V
NONE
SH1
SH2
BOTH
RES
Active
Active
Trip
Monitoring trip