KS8995XA Micrel Inc, KS8995XA Datasheet
KS8995XA
Specifications of KS8995XA
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KS8995XA Summary of contents
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... General Description The KS8995XA is a highly integrated Layer-2 quality of service (QoS) switch with optimized bill of materials (BOM) cost for low port 10/100Mbps switch systems. It also provides an extensive feature set including three different QoS priority schemes, a dual MII interface for BOM cost ...
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... Integrated look-up engine with dedicated 1K unicast MAC addresses Ordering Information Part Number Temperature Range Standard Pb-Free KS8995XA KSZ8995XA September 2008 • Automatic address learning, address aging and address migration • Full-duplex IEEE 802.3x and half-duplex back pressure flow control • Comprehensive LED support • ...
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Revision History Revision Date Summary of Changes 2.0 10/15/03 Created. 2.1 4/1/04 Editorial changes on TTL input and output electrical characteristics. 2.2 1/19/05 Insert recommended reset circuit. 2.3 4/13/05 Switched pins names for pins 7 & page 16. ...
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Contents System Level Applications........................................................................................................................................... 6 Pin Configuration .......................................................................................................................................................... 8 Pin Description (by Number)........................................................................................................................................ 9 Pin Description (by Name) ......................................................................................................................................... 14 Introduction ................................................................................................................................................................. 19 Functional Overview: Physical Layer Transceiver .................................................................................................. 19 100BASE-TX Transmit.............................................................................................................................................. 19 100BASE-TX Receive............................................................................................................................................... 19 PLL Clock Synthesizer.............................................................................................................................................. 19 ...
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Register 11 (0x0B): Global Control 9 ........................................................................................................................ 34 Port Registers ........................................................................................................................................................... 35 Register 16 (0x10): Port 1 Control 0 ......................................................................................................................... 35 Register 17 (0x11): Port 1 Control 1 ......................................................................................................................... 35 Register 18 (0x12): Port 1 Control 2 ......................................................................................................................... 36 Register ...
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... System Level Applications September 2008 Figure 1. Broadband Gateway MII-SW CPU KS8995XA Ethernet MAC Figure 2. Integrated Broadband Router 6 10/100 10/100 MAC 1 PHY 1 10/100 10/100 4-port PHY 2 MAC 2 LAN 10/100 10/100 PHY 3 MAC 3 10/100 10/100 PHY 4 MAC 4 10/100 10/100 MAC 5 PHY 5 EEPROM EEPROM ...
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September 2008 Figure 3. Standalone Switch 7 M9999-091508 ...
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Pin Configuration 103 LED2-0 LED1-2 LED1-1 LED1-0 MDC MDIO SPIQ SPIC/SCL SPID/SDA SPIS_N PS1 PS0 RST_N GNDD VDDC TESTEN SCANEN VDDAP GNDA VDDAR GNDA GNDA TEST2 1 September 2008 128-Pin PQFP (PQ PMRXD1 PMRXD2 PMRXD3 ...
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Pin Description (by Number) Pin Number Pin Name 1 MDI-XDIS 2 GNDA 3 VDDAR 4 RXP1 5 RXM1 6 GNDA 7 TXP1 8 TXM1 9 VDDAT 10 RXP2 11 RXM2 12 GNDA 13 TXP2 14 TXM2 15 VDDAR 16 GNDA ...
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Pin Number Pin Name 31 VDDAR 32 RXP5 33 RXM5 34 GNDA 35 TXP5 36 TXM5 37 VDDAT 38 FXSD5 39 FXSD4 40 GNDA 41 VDDAR 42 GNDA 43 VDDAR 44 GNDA MUX1 MUX2 ...
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Pin Number Pin Name 61 PMRXDV 62 PMRXD3 63 PMRXD2 64 PMRXD1 65 PMRXD0 66 PMRXER 67 PCRS 68 PCOL 69 SMTXEN 70 SMTXD3 71 SMTXD2 72 SMTXD1 73 SMTXD0 74 SMTXER 75 SMTXC 76 GNDD 77 VDDIO 78 SMRXC ...
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Pin Number Pin Name 86 SCONF1 87 SCONF0 88 GNDD 89 VDDC 90 LED5-2 91 LED5-1 92 LED5-0 93 LED4-2 94 LED4-1 95 LED4-0 96 LED3-2 97 LED3-1 98 LED3-0 99 GNDD 100 VDDIO 101 LED2-2 102 LED2-1 103 LED2-0 ...
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... All Output clock at 81kHz in I I/O All Serial data input/output in I All No connect Ipd No connect or pull-down. Ipd No connect or pull-down. Ipu Reset the KS8995XA. Active low. Gnd Digital ground. P 1.8V digital core V Ipd Factory test pin. Ipd Factory test pin connection. I 25MHz crystal clock connection/or 3.3V tolerant oscillator input. ...
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Pin Description (by Name) Pin Number Pin Name 39 FXSD4 38 FXSD5 2 GNDA 6 GNDA 12 GNDA 16 GNDA 21 GNDA 27 GNDA 30 GNDA 34 GNDA 40 GNDA 42 GNDA 44 GNDA 120 NC 124 GNDA 126 GNDA ...
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Pin Number Pin Name 96 LED3-2 95 LED4-0 94 LED4-1 93 LED4-2 92 LED5-0 91 LED5-1 90 LED5-2 107 MDC 108 MDIO MUX1 MUX2 68 PCOL 67 PCRS 60 PMRXC 65 PMRXD0 64 PMRXD1 ...
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Pin Number Pin Name 47 PWRDN_N 48 RESERVE/NC 109 Reserved 112 Reserved 115 RST_N 5 RXM1 11 RXM2 20 RXM3 26 RXM4 33 RXM5 4 RXP1 10 RXP2 19 RXP3 25 RXP4 32 RXP5 119 SCANEN 110 SCL 84 SCOL ...
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Pin Number Pin Name 82 SMRXD1 81 SMRXD2 80 SMRXD3 79 SMRXDV 75 SMTXC 73 SMTXD0 72 SMTXD1 71 SMTXD2 70 SMTXD3 69 SMTXEN 74 SMTXER 1 MDIXDIS 128 TEST2 118 TESTEN 7 TXP1 13 TXP2 22 TXP3 28 TXP4 ...
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Pin Number Pin Name 9 VDDAT 18 VDDAT 24 VDDAT 37 VDDAT 50 VDDC 89 VDDC 117 VDDC 59 VDDIO 77 VDDIO 100 VDDIO 121 X1 122 X2 Notes Power supply Input Output. ...
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... The major enhancements from the KS8995E to the KS8995XA are support for programmable rate limiting, a dual MII interface, MDC/MDIO control interface for IEEE 802.3-defined register configuration (not all the registers), per-port broadcast storm protection, local loopback and lower power consumption ...
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... Power Management The KS8995XA features a per port power down mode. To save power the user can power down ports that are not in use by setting port control registers or MII control registers. In addition, it also supports full chip power down mode. ...
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... The internal look-up table stores MAC addresses and their associated information. It contains a 1K unicast address table plus switching information. The KS8995XA is guaranteed to learn 1K addresses and distinguishes itself from hash-based look-up tables which, depending on the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn ...
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... The KS8995XA will flow control a port, which just received a packet, if the destination port resource is being used up. The KS8995XA will issue a flow control frame (XOFF), containing the maximum pause time defined in IEEE standard 802 ...
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... Broadcast packets will be forwarded to all ports except the source port, and thus use too many switch resources (bandwidth and available space in transmit queues). The KS8995XA has the option to include “multicast packets” for storm control. The broadcast storm rate parameters are programmed globally, and can be enabled or disabled on a per port basis ...
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... MTXER would indicate a transmit error from the MAC device. These signals are not appropriate for this configuration. For PHY mode operation, if the device interfacing with the KS8995XA has an MRXER pin, it should be tied low. For MAC mode operation, if the device interfacing with the KS8995XA has an MTXER pin, it should be tied low. ...
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... SMRXD[3] Receive data bit 3 SMRXD[2] Receive data bit 2 SMRXD[1] Receive data bit 1 SMRXD[0] Receive data bit 0 SMRXC Receive clock Table 2. MII – SW Signals 25 MAC Mode Connection KS8995XA External PHY Signal MTXEN SMRXDV MTXER Not used MTXD3 SMRXD[3] MTXD2 SMRXD[2] MTXD1 SMRXD[1] ...
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... Each port on the KS8995XA can be set as high or low priority with an EEPROM. The port priority is set in bit 4 of registers 0x10, 0x20, 0x30, 0x40, 0x50 for ports and 5, respectively. Port-based priority is overridden by the OR’ed result of the 802 ...
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... DiffServ classification is enabled on a per port basis in bit 6 of registers 0x10, 0x20, 0x30, 0x40 and 0x50 for ports and 5, respectively. If the DiffServ classification is enabled on a port, the KS8995XA will decode the IPv4 DiffServ field and look at the user defined code point bit to determine if the packet is high priority or low priority. If the code point is a ‘ ...
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... The rate limit starts from 0Kbps and goes up to the line rate in steps of 32Kbps. The KS8995XA uses one second as an interval. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number of bytes during this interval. ...
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... SDA To configure the KS8995XA with a pre-configured EEPROM use the following steps: • At the board level, connect pin 110 on the KS8995XA to the SCL pin on the EEPROM. Connect pin 111 on the KS8995XA to the SDA pin on the EEPROM. • Be sure the board-level reset signal is connected to the KS8995XA reset signal on pin 115 (RST_N). ...
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Register Map Offset Decimal Hex Description 0-1 0x00-0x01 Chip ID Registers 2-11 0x02-0x0B Global Control Registers 12-15 0x0C-0x0F Reserved 16-29 0x10-0x1D Port 1 Control Registers 30-31 0x1E-0x2F Port 1 Status Registers 32-45 0x20-0x2D Port 2 Control Registers 46-47 0x2E-0x2F Port ...
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Address Name 3 Enable PHY MII 2 Buffer share mode 1 UNH mode 0 Link change age Register 3 (0x03): Global Control 1 7 Pass all frames 6 Reserved 5 IEEE 802.3x transmit flow control disable 4 IEEE 802.3x receive ...
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Address Name 0 Aggressive back off enable Register 4 (0x04): Global Control 2 7 Reserved 6 Multicast storm protection disable 5 Reserved 4 Flow control and back pressure fair mode 3 No excessive collision drop 2 Huge packet support 1 ...
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Address Name 0 Priority buffer reserve Register 5 (0x05): Global Control 3 7 Reserved 6 Reserved 5 Reserved 4 Reserved 3-2 Priority scheme select 1 Reserved 0 Sniff mode select Register 6 (0x06): Global Control 4 7 Switch MII back ...
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Address Name Register 7 (0x07): Global Control 5 7-0 Broadcast storm protection rate bit [7:0] Register 8 (0x08): Global Control 6 7-0 Factory testing Register 9 (0x09): Global Control 7 7-0 Factory testing Register 10 (0x0A): Global Control 8 7-0 ...
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Port Registers The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are the same for all ports, but the address for each port is different, as indicated. Register 16 ...
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Address Name 7 Sniffer port 6 Receive sniff 5 Transmit sniff 4-0 Port VLAN membership Register 18 (0x12): Port 1 Control 2 Register 34 (0x22): Port 2 Control 2 Register 50 (0x32): Port 3 Control 2 Register 66 (0x42): Port ...
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Address Name 0 Learning disable Register 19 (0x13): Port 1 Control 3 Register 35 (0x23): Port 2 Control 3 Register 51 (0x33): Port 3 Control 3 Register 67 (0x43): Port 4 Control 3 Register 83 (0x53): Port 5 Control 3 ...
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Address Name 7-0 Transmit low priority rate control [7:0] Register 23 (0x17): Port 1 Control 7 Register 39 (0x27): Port 2 Control 7 Register 55 (0x37): Port 3 Control 7 Register 71 (0x47): Port 4 Control 7 Register 87 (0x57): ...
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Register 26 (0x1A): Port 1 Control 10 Register 42 (0x2A): Port 2 Control 10 Register 58 (0x3A): Port 3 Control 10 Register 74 (0x4A): Port 4 Control 10 Register 90 (0x5A): Port 5 Control 10 Address Name 7-4 Receive low ...
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Address Name 0 High priority transmit rate control enable Register 28 (0x1C): Port 1 Control 12 Register 44 (0x2C): Port 2 Control 12 Register 60 (0x3C): Port 3 Control 12 Register 76 (0x4C): Port 4 Control 12 Register 92 (0x5C): ...
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Address Name 7 LED off 6 Txids 5 Restart AN 4 Disable far end fault 3 Power down 2 Disable auto MDI/MDI-X 1 Forced MDI 0 MAC loopback Register 30 (0x1E): Port 1 Status 0 Register 46 (0x2E): Port 2 ...
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Address Name 7 PHY loopback 6 Remote loopback 5 PHY isolate 4 Soft reset 3 Force link 2-1 Reserved 0 Far end fault September 2008 Description 1, perform PHY loopback, i.e. loopback MAC’s Tx back to Rx. 0, normal operation. ...
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Advanced Control Registers The IPv4 TOS priority control registers implement a fully decoded 64 bit differentiated services code point (DSCP) register used to determine priority from the 6 bit TOS field in the IP header. The most significant 6 bits ...
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MIIM Registers The “PHYAD” defined by IEEE is assigned as “0x1” for port 1, “0x2” for port 2, “0x3” for port 3, “0x4” for port 4, “0x5” for port 5. The “REGAD” supported are 0,1,2,3,4,5. Address Name Register 0: MII ...
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Address Name 2 Link status 1 Jabber test 0 Extended capable Register 2: PHYID HIGH 15-0 Phyid high Register 3: PHYID LOW 15-0 Phyid low Register 4: Advertisement Ability 15 Next page 14 Reserved 13 Remote fault 12-11 Reserved 10 ...
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Absolute Maximum Ratings Supply Voltage ( .......................–0.5V to +2.4V DDAR DDAP DDC ( .................................–0.5V to +4.0V DDAT DDIO Input Voltage (All Inputs) ......................–0.5V to +4.0V Output Voltage (All Outputs) ................–0.5V to +4.0V ...
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Symbol Parameter 10BASE-T Receive V Squelch Threshold SQ 10BASE-T Transmit (measured differentially after 1:1 transformer Peak Differential Output Voltage P Jitters Added Rise/Fall Times Notes: 1. Exceeding the absolute maximum rating may damage the device. 2. The device ...
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Timing Diagrams Receive Timing SCL SDA Figure 9. EEPROM Interface Input Receive Timing Diagram Transmit Timing SCL SDA Figure 10. EEPROM Interface Output Transmit Timing Diagram Symbol Parameter t Clock Cycle CYC1 t Set-Up Time S1 t Hold Time H1 ...
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Receive Timing MTXC MTXEN MTXD[0] Transmit Timing MRXC MRXDV MCOL MRXD[0] Symbol Parameter t Clock Cycle CYC2 t Set-Up Time S2 t Hold Time H2 t Output Valid O2 September 2008 ts2 tcyc2 th2 Figure 11. SNI Input Timing tcyc2 ...
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Symbol Parameter t RXC Period P t RXC Pulse Width WL t RXC Pulse Width WH t RXD [3:0], RXDV Set-up to Rising Edge of RXC SU t RXD [3:0], RXDV Hold from Rising Edge of RXC HD t CRS ...
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Symbol Parameter t TXD [3:0] Set-up to TXC High SU1 t TXEN Set-up to TXC High SU2 t TXD [3:0] Hold after TXC High HD1 t TXER Hold after TXC High HD2 t TXEN High to CRS Asserted Latency CRS1 ...
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Supply Voltage RST_N Strap-In Value Strap-In / Output Pin Symbol Parameter t Stable Supply Voltages to Reset High SR t Configuration Set-Up Time CS t Configuration Hold Time CH t Reset to Strap-In Pin Output RC September 2008 tsr tcs ...
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... CPU/FPGA provides warm reset after power up also recommended to power up the VDD core voltage earlier than VDDIO voltage. At worst case, the both VDD core and VDDIO voltages should come up at the same time. September 2008 VCC D1: 1N4148 D1 KS8995XA RST 10µF Figure 16. Recommended Reset Circuit VCC R ...
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Selection of Isolation Transformer One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common- mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Characteristics Name Turns Ratio ...
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Package Information MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no ...