DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 195

IC TRPL ATM/PACKET PHY 400-PBGA

DS3163

Manufacturer Part Number
DS3163
Description
IC TRPL ATM/PACKET PHY 400-PBGA
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS3163

Applications
*
Mounting Type
Surface Mount
Package / Case
400-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Table 11-1. Global and Test Register Address Map
000 - 01F
020 – 02F
030 – 037
038 - 03F
040 – 1FF
200 – 23F
240 – 3FF
400 – 43F
440 – 5FF
600 – 63F
640 – 6FF
Each port has a relative address range of 040h to 1FFh. The lower 000h to 03Fh address range is used for global,
test and reserved registers. The following table is a map of the registers for each port. The address offset is from
the start of each port range of 000h, 200h, 400h and 600h. In a DS3163, writes to registers in port 4 will be ignored
and reads from port 4 registers will read back zero values. Similarly, in a DS3161, writes to registers in port 2 will
be ignored and reads from port 2 will read back zero values.
NOTE: The RDY signal will not go active if the user attempts to read or write unused ports or unused registers not
assigned to any design blocks. The RDY signal will go active if the user writes or reads reserved registers or
unused registers within design blocks.
Address
Global registers, Section
Unused
UTOPIA/POS-PHY Transmit System bus, Section
UTOPIA/POS-PHY Receive System bus, Section
Port 1 Register Map
Test Registers
Port 2 Register Map
Test Registers
Port 3 Register Map
Unused
Port 4 Register Map
Description
12.1
12.3.2
12.3

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