DS1875T+T&R Maxim Integrated Products, DS1875T+T&R Datasheet - Page 82
DS1875T+T&R
Manufacturer Part Number
DS1875T+T&R
Description
IC SFP CTRLR/TRIPLEXER 38-TQFN
Manufacturer
Maxim Integrated Products
Datasheet
1.DS1875TTR.pdf
(92 pages)
Specifications of DS1875T+T&R
Applications
Fiber Optics
Interface
I²C
Voltage - Supply
2.85 V ~ 3.9 V
Package / Case
*
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PON Triplexer and SFP Controller
Table 02h, Register C5h to C6h: RESERVED
Table 02h, Register C7h: M4 LUT CNTL
82
______________________________________________________________________________________
C7h
FACTORY DEFAULT
READ ACCESS
WRITE ACCESS
MEMORY TYPE
FACTORY DEFAULT
READ ACCESS
WRITE ACCESS
MEMORY TYPE
These registers are reserved.
Controls the size and location of LUT functions for the MON4 measurement.
RESERVED
BITS 7:4
BITS 3:2
BIT 7
BIT 1
BIT 0
RESERVED (Default = 000000b)
FBOL and FBCL: Force bias open loop and force bias closed loop.
00b = (Default) normal operation.
10b = Force control of I
01b = Force control of I
11b = Same as 10b.
When forcing open-loop mode, BEN should be ground or at any burst length.
DBL_SB: Chooses the size of LUT for Table 06h.
0 = (Default) Single LUT of 32 bytes.
1 = Double LUT of 16 bytes.
UP_LOWB: Determines which 16-byte LUT is used if DBL_SB = 1. If DBL_SB = 0, the value of
this bit is a don’t care.
0 = (Default) Chooses the lower 16 bytes of Table 06h (80h to 8Fh).
1 = Chooses the upper 16 bytes of Table 06h (90h to 9Fh).
RESERVED
00h
PW2
PW2
Nonvolatile (SEE)
00h
PW2
PW2
Nonvolatile (SEE)
RESERVED
BIAS
BIAS
to be open loop regardless of duration of BEN pulses.
to be closed loop regardless of duration of BEN pulses.
RESERVED
FBOL
FBCL
DBL_SB
UP_LOWB
BIT 0
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