KSZ8695P Micrel Inc, KSZ8695P Datasheet - Page 29

• Manufacturer Part Number: KSZ8695P
• Description: IC ARM9 W/MMU PHY 10/100 289PBGA
• Manufacturer: Micrel Inc

Specifications of KSZ8695P

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 289-PBGA
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.7/3V
• Operating Supply Voltage (max): 1.9/3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 289
• For Use With: 576-1623 - BOARD EVALUATION KSZ8695P-MMB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-1509-5; KSZ8695P

General Purpose I/O Pins (continued)
Micrel, Inc.
May 2006
C15
D14
D10
C10
C11
D11
A15
A16
A11
B11
A10
Pin
A6
B9
C8
A9
D7
E4
DEVSELN
FRAMEN
TRDYN
STOPN
PERRN
SERRN
CBEN3
CBEN2
CBEN1
CBEN0
M66EN
IRDYN
IDSEL
Name
PAD2
PAD1
PAD0
PAR
I/O Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
(1)
Description
32-Bit PCI address and data (continued from previous page).
PCI commands and byte enable. Active low.
The PCI command and byte enable signals are multiplexed on the same pins.
During the first clock cycle of a PCI transaction, the CBEN bus contains the
command for the transaction. The PCI transaction consists of the address phases
and one or more data phases. During the data phases of the transaction, the bus
carries the byte enable for the current data phases.
Parity. PCI bus parity is even across PAD[31:0] and CBEN[3:0]. The KS8695P
generates PAR during the address phase and write data phases as a bus master
and during read data phases as a target. It checks for correct PAR during the read
data phase as a bus master, during every address phase as a bus slave, and during
write data phases as a target.
PCI bus frame signal. Active low. FRAMEN is an indication of an active PCI bus
cycle. It is asserted at the beginning of a PCI transaction, i.e. the address phase,
and deasserted before the final transfer of the data phase of the transaction.
PCI initiator ready signal. Active low. This signal is asserted by a PCI master to
indicate a valid data phase on the PAD bus during data phases of a write
transaction. During a read transaction, it indicates that the master is ready to accept
data from the target. A target monitors the IRDYN signal when a data phase is
completed on any rising edge of the PCI clock when both IRDYN and TRDYN are
asserted. Wait cycles are inserted until both IRDYN and TRDYN are asserted
together.
PCI target ready signal. Active low. This signal is asserted by a PCI slave to
indicate a valid data phase on the PAD bus during a read transaction. During a write
transaction, it indicates that the slave is ready to accept data from the target. A PCI
initiator monitors the TRDYN signal when a data phase is completed on any rising
edge of the PCI clock when both IRDYN and TRDYN are asserted. Wait cycles are
inserted until both IRDYN and TRDYN are asserted together.
PCI device select signal. Active low. This signal is asserted when the KS8695P is
selected as a target during a bus transaction. When the KS8695P is the initiator of
the current bus access, it expects the target to assert DEVSELN within fi ve PCI bus
cycles, confirming the access. If the target does not assert DEVSELN within the
required bus cycles, the KS8695P aborts the bus cycle. To meet the timing
requirement, the KS8695P asserts this signal in a medium speed decode timing.
(two bus cycles).
Initialization device select. Active high. It is used as a chip select during
configuration read and write transactions.
PCI stop signal. Active low. This signal is asserted by the PCI target to indicate to
the bus master that it is terminating the current transaction. The KS8695P responds
to the assertion of STOPN when it is the bus master, either to disconnect, retry, or
abort the transaction.
PCI parity error signal. Active low. The KS8695P asserts PERRN when it checks
and detects a bus parity error. When it generates the PAR output, the KS8695P
monitors for any reported parity error on PERRN. When the KS8695P is the bus
master and a parity error is detected, the KS8695P sets error bits in the control
status registers. It completes the current data burst transaction, and then stops the
operation. After the host clears the system error, the KS8695P continues its
operation.
PCI system error signal. Active low. If an address parity error is detected, the
KS8695P asserts the SERRN signal two clocks after the failing address.
PCI 66MHz enable. When asserted, this signal indicates the PCI bus segment is
operating at 66MHz. This pin is mainly used in guest bridge mode when the PCLK
is driven by an external host bridge.
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M9999-051806
KS8695P