NCP1580DR2 ON Semiconductor, NCP1580DR2 Datasheet - Page 7

• Manufacturer Part Number: NCP1580DR2
• Description: IC CTLR SYNCH BUCK LV 8-SOIC
• Manufacturer: ON Semiconductor
• Type: Step-Down (Buck)r

Specifications of NCP1580DR2

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: Adj to 0.8V
• Frequency - Switching: 350kHz
• Voltage - Input: 4.5 ~ 13.2 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Topology: Buck
• Output Voltage: 0.8 V
• Output Current: 1500 mA
• Switching Frequency: 412 KHz
• Duty Cycle (max): 95 %
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Fall Time: 15 ns
• Mounting Style: SMD/SMT
• Rise Time: 6 ns
• Synchronous Pin: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output: -
• Power - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

UVLO
unexpected behavior does not occur when V
support the internal rails and power the converter. For the
NCP1580, the UVLO is set to ensure that the IC will start up
when V
below 3.7 V. This permits operation when converting from
a 5.0 V input voltage.
Thermal Shutdown
for added protection. The TSD circuit monitors the die
temperature and turns off the top and bottom gate drivers if
an over temperature condition is detected. The internal soft−
start capacitor is also discharged. This is a latched state and
requires a power cycle to reset.
Undervoltage Lockout (UVLO) is provided to ensure that
The NCP1580 also provides Thermal Shutdown (TSD)
CC
reaches 4.2 V and shutdown when V
PWM
OUT
FAULT
UVLO
CC
is too low to
Figure 12. Block Diagram
CC
http://onsemi.com
drops
UVLO
FAULT
NCP1580
−
−
+
+
7
2 V
2 V
Drivers
external N−Channel MOSFETs. This allows the NCP1580
to address high−power as well as low−power conversion
requirements. The gate drivers also include adaptive
non−overlap circuitry. The non−overlap circuitry increases
efficiency, which minimizes power dissipation, by
minimizing the body diode conduction time.
drive circuitry used in the chip is shown in Figure 12.
required, to realize the full benefit of the onboard drivers.
The capacitors between V
and SWN must be placed as close as possible to the IC. The
current paths for the TG and BG connections must be
optimized. A ground plane should be placed on the closest
layer for return currents to GND in order to reduce loop area
and inductance in the gate drive circuit.
The NCP1580 includes 1.5 A gate drivers to switch
A detailed block diagram of the non−overlap and gate
Careful selection and layout of external components is
BST
TG
PHASE
V
BG
GND
CC
CC
and GND and between BST