LM5118Q1MH/NOPB National Semiconductor, LM5118Q1MH/NOPB Datasheet - Page 20

• Manufacturer Part Number: LM5118Q1MH/NOPB
• Description: IC BUCK BST ADJ 20TSSOP
• Manufacturer: National Semiconductor
• Series: PowerWise®r
• Type: Step-Down (Buck), Step-Up (Boost)r

Specifications of LM5118Q1MH/NOPB

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 1.23 ~ 70 V
• Frequency - Switching: 200kHz, 515kHz
• Voltage - Input: 3 ~ 75 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP Exposed Pad, 20-eTSSOP, 20-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Power - Output: -
• Other names: *LM5118Q1MH/NOPB; LM5118Q1MH

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be located close to the RHP zero. The error amplifier zero
(see below) should be placed near the dominate modulator
pole. This is a good starting point for compensation. Refer to
the on-line LM5118 Quick-Start calculator for ready to use
equations and more details.
Components R4 and C18 configure the error amplifier as a
type II configuration which has a DC pole and a zero at
C17 introduces an additional pole used to cancel high fre-
quency switching noise. The error amplifier zero cancels the
modulator pole leaving a single pose response at the
crossover frequency of the loop gain if the crossover frequen-
cy is much lower than the right half plane zero frequency. A
single pole response at the crossover frequency yields a very
stable loop with 90 degrees of phase margin.
For the design example, a target loop bandwidth (crossover
frequency) of 2.0 kHz was selected (about 30% of the right-
FIGURE 14. Error Amplifier Gain and Phase
FIGURE 13. Modulator Gain and Phase
20
half-plane zero frequency). The error amplifier zero (fz)
should be selected at a frequency near that of the modulator
pole and much less than the target crossover frequency. This
constrains the product of R4 and C18 for a desired compen-
sation network zero to be less than 2 kHz. Increasing R4,
while proportionally decreasing C18 increases the error amp
gain. Conversely, decreasing R4 while proportionally increas-
ing C18 decreases the error amp gain. For the design exam-
ple C18 was selected for 4.7 nF and R4 was selected to be
10 kΩ. These values set the compensation network zero at
149 Hz. The overall loop gain can be predicted as the sum (in
dB) of the modulator gain and the error amp gain.
If a network analyzer is available, the modulator gain can be
measured and the error amplifier gain can be configured for
the desired loop transfer function. If a network analyzer is not
available, the error amplifier compensation components can
be designed with the guidelines given. Step load transient
tests can be performed to verify acceptable performance. The
step load goal is minimal overshoot with a damped response.
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