LP3907TLX-JSXS/NOPB National Semiconductor, LP3907TLX-JSXS/NOPB Datasheet - Page 25
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LP3907TLX-JSXS/NOPB
Manufacturer Part Number
LP3907TLX-JSXS/NOPB
Description
IC PMU DUAL DC/DC REG 25USMD
Manufacturer
National Semiconductor
Series
PowerWise®r
Type
Step-Down (Buck)r
Datasheet
1.LP3907SQ-JXQXNOPB.pdf
(46 pages)
Specifications of LP3907TLX-JSXS/NOPB
Topology
Step-Down (Buck) Synchronous (2), Linear (LDO) (2)
Function
Any Function
Number Of Outputs
4
Frequency - Switching
2.1MHz
Voltage/current - Output 1
1.2V, 1A
Voltage/current - Output 2
2.8V, 600mA
Voltage/current - Output 3
3.3V, 300mA
W/led Driver
No
W/supervisor
No
W/sequencer
Yes
Voltage - Supply
2.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
25-MicroSMD
Current - Output
300mA, 600mA, 1A
Voltage - Output
1.2V, 2.8V
Voltage - Input
2.8 ~ 5.5 V
Power - Output
1.43W
Internal Switch(s)
Yes
Synchronous Rectifier
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
LP3907TLX-JSXS
Flexible Power-On Reset (i.e., Power
Good with delay)
The LP3907 is equipped with an internal Power-On-Reset
(“POR”) circuit which monitors the output voltage levels on
bucks 1 and 2. The nPOR is an open drain logic output which
The above diagram shows the simplest application of the
Power On Reset, where both switcher enables are tied to-
gether. In Case 1, EN1 causes nPOR to transition LOW and
triggers the nPOR delay counter. If the power supply for
Buck2 does not come on within that period, nPOR will stay
LOW, indicating a power fail mode. Case 2 indicates the vice
NPOR With Counter Delay
25
is logic LOW when either of the buck outputs are below 91%
of the rising value , or when one or both outputs fall below
82% of the desired value. The time delay between output
voltage level and nPOR is enabled is (50µs, 50ms, 100ms,
200ms) 50ms by default. The system designer can choose
the external pull-up resistor (i.e. 100kΩ) for the nPOR pin.
versa scenario if Buck1 supply did not come on. In both cases
the nPOR remains LOW.
Case 3 shows a typical application of the Power On Reset,
where both switcher enables are tied together. Even if RDY1
ramps up slightly faster than RDY2 (or vice versa), then nPOR
signal will trigger a programmable delay before going HIGH,
as explained below.
30017821
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