IP2005APBF International Rectifier, IP2005APBF Datasheet

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IP2005APBF

Manufacturer Part Number
IP2005APBF
Description
IC PWR BLOCK SYNC BUCK 40A LGA
Manufacturer
International Rectifier
Series
iPOWIR™r
Type
Step-Down (Buck)r
Datasheet

Specifications of IP2005APBF

Internal Switch(s)
Yes
Synchronous Rectifier
Yes
Number Of Outputs
1
Voltage - Output
0.8 ~ 5.5 V
Current - Output
40A
Frequency - Switching
250kHz ~ 1.5MHz
Voltage - Input
6.5 ~ 13.2 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
Power Block (LGA)
Power - Output
9.3W
Package
LGA - 7.7 x 7.7
Circuit
Power Stage
Iout (a)
40
Switch Freq (khz)
250 - 1500
Input Range (v)
6.5 - 13.2
Output Range (v)
0.8 - 5.5
Ocp Otp Uvlo Pre-bias Soft Start And
UVLO (no OVP OCP OTP nor Soft Start)
Pbf
PbF Option Available
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IP2005APBF
Manufacturer:
TOSHIBA
Quantity:
68
Part Number:
IP2005APBF
Manufacturer:
IR
Quantity:
20 000
Applications
Features
www.irf.com
iP2005APbF
iP2005ATRPbF
Typical Application
Description
High Frequency, Low Profile DC-DC
Multi-phase Architectures
Low Duty Cycle, High Current solutions
Microprocessor Power Supplies
General DC/DC Converters
40A Multiphase building block
No de-rating up to T
Optimized for low power loss
Optimized for low EMI
Bias supply range of 4.5V to 7.0V
Operation up to 1.5MHz
Bi-directional Current flow
Under Voltage Lockout
LGA interface
7.65mm x 7.65mm outline
Package
Connection
Interface
LGA
LGA
PCB
Standard
Quantity
2000
= 95ºC
Integrated Power Semiconductors, Driver IC, & Passives
10
Orientation
Figure 15
High Frequency Synchronous Buck
T & R
N/A
2/8/2008
Description
The iP2005A is a fully optimized solution for high current
synchronous buck multiphase applications. Board space
and design time are greatly reduced because most of
the components required for each phase of a typical
discrete-based multiphase circuit are integrated into a
single 7.65mm x 7.65mm x 1.66mm power block. The
additional
multiphase converter are a PWM controller, the output
inductors, and the input and output capacitors.
iPOWIR Technology offers designers an innovative
board space saving solution for applications requiring
high power densities. iPOWIR technology eases design
for applications where component integration offers
benefits in performance and functionality.
technology solutions are also optimized internally for
layout, heat transfer, and component selection.
Optimized LGA Power Stage
94
92
90
88
86
84
82
80
78
76
74
72
70
4
6
components
8
10
V
IN
iP2005A Product Efficiency
12
= 12V, F
14
16
SW
18
Output Current (A)
iP2005APbF
required
= 1MHz, & T
20
22
24
26
for
BLK
28
PD-60325
= 125ºC
30
a
32
34
complete
Vo = 3.3V
Vo = 2.5V
Vo = 1.8V
Vo = 1.3V
iPOWIR
36
38
40
1

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IP2005APBF Summary of contents

Page 1

... T & R Orientation benefits in performance and functionality. 10 N/A technology solutions are also optimized internally for Figure 15 layout, heat transfer, and component selection 2/8/2008 iP2005APbF components required for iP2005A Product Efficiency V = 12V 1MHz, & BLK ...

Page 2

... Input Voltage ( Output Voltage (V ) OUT Output Current (I ) OUT Switching Frequency On Time Duty Cycle Minimum V On Time SW Block Temperature (T ) BLK www.irf.com ) MIN TYP MAX 4.5 - 7.0 6 250 - 1500 - - -40 - 125 2/8/2008 PD-60325 iP2005APbF UNITS CONDITIONS kHz % 5.0V 12V DD IN ºC (Note 2) 2 ...

Page 3

... PD-60325 iP2005APbF UNITS CONDITIONS V = 12V 5.0V 1.3V, I OUT OUT 1MHz 0.3uH, T OUT BLK (Note 5.0, ENABLE = 12V, ENABLE = 1MHz, 10 µF Ceramic, X5R, 16V Rising & ...

Page 4

... PGND pins (see Figure 8) 4. Not associated with rise and fall times. Does not affect Power Loss www.irf.com = 0ºC to 125ºC and V = 5.0V unless otherwise specified. BLK DD MIN TYP MAX - - 0.8 2 100 - - 100 - - 2/8/2008 PD-60325 iP2005APbF UNITS CONDITIONS Schmitt Trigger Input V = POR to 7.0V kΩ DD (Note ...

Page 5

... Power Loss Curve SOA Curve www.irf.com Figure 1 Power Loss Curve Figure 2 Safe Operating Area Curve 2/8/2008 PD-60325 iP2005APbF 5 ...

Page 6

... Figure 6 Normalized Power Loss vs. Switching Frequency Supply Current vs. Switching Frequency DD 2/8/2008 PD-60325 iP2005APbF = 12. 5. 40A OUT = 1MHz SW = 300nH = 125ºC 1.3 1.8 2.3 2.8 Output Voltage (V) = 12. ...

Page 7

... Figure 8 Power Loss Test Circuit Figure 9 Timing Diagram 2/8/2008 PD-60325 iP2005APbF 7 ...

Page 8

... Current). The point at which the horizontal line meets the Y-axis is the SOA continuous current 12. 5. 1.3V OUT F = 1MHz 300nH OUT Figure 10 SOA Example, Continuous current ≈ 31A for T www.irf.com axis intercept to the SOA curve. X PCB 2/8/2008 PD-60325 iP2005APbF = 100ºC & 110ºC CASE 8 ...

Page 9

... Maximum power loss = 9.0W Normalized power loss for input voltage ≈ 0.95 Normalized power loss for output voltage ≈ 1.0 Normalized power loss for output inductor ≈ 1.026 Normalized power loss for switch frequency ≈ 0.87 2/8/2008 PD-60325 iP2005APbF axis intercept in Figure ...

Page 10

... SOA temperature adjustment for output voltage ≈ 0.0ºC SOA temperature adjustment for output inductor ≈ 0.6 ºC SOA temperature adjustment for switch frequency ≈ -3.5 ºC = 110ºC CASE axis intercept to the SOA curve. X axis by adding or subtracting the SOA adjustment X intercept point. X 2/8/2008 PD-60325 iP2005APbF decrease of 4.1º ...

Page 11

... EMI. The figures above show waveform comparisons of switching node voltages of the previous generation iP2003A product and iP2005A under equivalent operation conditions. www.irf.com 5V/div 20nS/div Vsw of iP2005A 2/8/2008 PD-60325 iP2005APbF 11 ...

Page 12

... When set to logic level high, internal circuitry of the device is enabled. When set to logic level low, the Control and Synchronous FETs are turned off. Output of internal regulator. Attached a minimum of 1.0µF capacitance from this pin to PGND. Recommended to use 16V, X5R, Ceramic type capacitor. 2/8/2008 PD-60325 iP2005APbF 12 ...

Page 13

... Recommended PCB Layout Figure 12 Top copper and Solder-mask layer of PCB layout www.irf.com 2/8/2008 PD-60325 iP2005APbF 13 ...

Page 14

... Component Layer). In both cases, C2 – C5 need to be placed right underneath the iP2005A PCB footprint. • Dedicate at least two layer to for P • Duplicate the Power Nodes on multiple layers (refer to AN1029). www.irf.com , V , and GND only GND 2/8/2008 PD-60325 iP2005APbF ) for both electrical and 14 ...

Page 15

... Land patterns on user’s PCB should be an identical mirror image of the pattern shown in bottom view 2. Lands should be solder mask defined 3. All I/O pads on this product are metal finish with flash gold Figure 14 Mechanical Outline Drawing 2/8/2008 PD-60325 iP2005APbF BOTTOM VIEW 15 ...

Page 16

... Tape and Reel Information YYMM XXXX 2005AP www.irf.com YYMM XXXX 2005AP XX XX 12.00 (.473) FEED DIRECTION Figure 15 Tape and Reel Information 2/8/2008 PD-60325 iP2005APbF 16.00 (.630) 16 ...

Page 17

... Solid lines show PCB pad openings. 5.The recommended reflow peak temperature is 260ºC. The total furnace time is approximately 5 minutes with approximately 10 seconds at peak temperature. Part Marking www.irf.com Figure 16 Solder Paste Stencil Design Figure 17 Part Marking 2/8/2008 PD-60325 iP2005APbF 17 ...

Page 18

... N. Sepulveda Blvd., El Segundo, California 90245, USA Tel: (310) 252-7105 This product has been designed for the Industrial market. Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 12/24/2007 2/8/2008 PD-60325 iP2005APbF TAC Fax: (310) 252-7903 18 ...

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