LT1372CN8 Linear Technology, LT1372CN8 Datasheet - Page 10

• Manufacturer Part Number: LT1372CN8
• Description: IC SWTCHNG REG 1.5A HI-EFF 8-DIP
• Manufacturer: Linear Technology
• Type: Step-Down (Buck), Step-Up (Boost), Inverting, Cuk, Flyback, Forward Converterr

Specifications of LT1372CN8

• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 1.25 ~ 30 V
• Current - Output: 1.5A
• Frequency - Switching: 500kHz
• Voltage - Input: 2.7 ~ 25 V
• Operating Temperature: 0°C ~ 125°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

APPLICATIO S I FOR ATIO
LT1372/LT1377
10
Frequency Compensation
Loop frequency compensation is performed on the output
of the error amplifier (V
The main pole is formed by the series capacitor and the
output impedance ( 500k ) of the error amplifier. The
pole falls in the range of 2Hz to 20Hz. The series resistor
creates a “zero” at 1kHz to 5kHz, which improves loop
stability and transient response. A second capacitor,
typically one-tenth the size of the main compensation
capacitor, is sometimes used to reduce the switching
frequency ripple on the V
output voltage ripple attenuated by the output divider and
multiplied by the error amplifier. Without the second
capacitor, V
To prevent irregular switching, V
kept below 50mV
maximum output load current and will also be increased
if poor quality (high ESR) output capacitors are used. The
addition of a 0.0047 F capacitor on the V
switching frequency ripple to only a few millivolts. A low
value for R
margin may be inadequate.
Switch Node Considerations
For maximum efficiency, switch rise and fall time are
made as short as possible. To prevent radiation and high
frequency resonance problems, proper layout of the com-
ponents connected to the switch node is essential. B field
V
V
g
R
V
m
C
RIPPLE
OUT
C
Pin Ripple =
= Series resistor on V
= Error amplifier transconductance
( 1500 mho)
= DC output voltage
C
= Output ripple (V
C
will also reduce V
pin ripple is:
P–P
U
1.245(V
. Worst-case V
C
C
U
pin) with a series RC network.
pin. V
RIPPLE
(V
C
C
P–P
OUT
pin
pin ripple, but loop phase
C
C
pin ripple is caused by
)
W
)(g
)
C
pin ripple should be
pin ripple occurs at
m
)(R
C
C
)
pin reduces
U
More Help
For more detailed information on switching regulator
circuits, please see Application Note 19. Linear Technol-
ogy also offers a computer software program, SwitcherCAD,
to assist in designing switching converters. In addition,
our applications department is always ready to lend a
helping hand.
(magnetic) radiation is minimized by keeping output di-
ode, switch pin, and output bypass capacitor leads as
short as possible. E field radiation is kept low by minimiz-
ing the length and area of all traces connected to the switch
pin. A ground plane should always be used under the
switcher circuitry to prevent interplane coupling.
The high speed switching current path is shown schemati-
cally in Figure 3. Minimum lead length in this path is
essential to ensure clean switching and low EMI. The path
including the switch, output diode, and output capacitor is
the only one containing nanosecond rise and fall times.
Keep this path as short as possible.
V
IN
L1
SWITCH
NODE
CIRCULATING
Figure 3
FREQUENCY
PATH
HIGH
LOAD
LT1372 • F03
V
OUT