LTC3736EUF-1#TRPBF Linear Technology, LTC3736EUF-1#TRPBF Datasheet - Page 6

• Manufacturer Part Number: LTC3736EUF-1#TRPBF
• Description: IC CTRLR SW SYNC DUAL 2PH 24QFN
• Manufacturer: Linear Technology
• Series: PolyPhase®r
• Type: Step-Down (Buck)r

Specifications of LTC3736EUF-1#TRPBF

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: 0.6 ~ 9.8 V
• Current - Output: 1A
• Frequency - Switching: 450kHz ~ 580kHz
• Voltage - Input: 2.75 ~ 9.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

PI FU CTIO S
LTC3736-1
I
Error Amplifier Compensation Point. Nominal operating
range on these pins is from 0.7V to 2V. The voltage on
these pins determines the threshold of the main current
comparator.
FREQ (Pin 3/Pin 6): Frequency Filter and Adjust Pin. Nor-
mally, when spread spectrum operation is enabled (SSDIS
= GND), a capacitor (1nF to 4.7nF) is connected from this
pin to SGND or V
quency of the LTC3736-1’s internal oscillator.
When spread spectrum operation is disabled (SSDIS = V
this pin serves as a frequency adjust pin. In this mode, tying
this pin to GND selects 300kHz operation; tying this pin to
V
550kHz operation.
When spread spectrum operation is enabled (SSDIS =
GND), an external voltage between approximately 0.7V and
1.5V may be applied to this pin to adjust (in an analog
manner) the LTC3736-1’s frequency.
SGND (Pin 4/Pin 7): Small-Signal Ground. This pin serves
as the ground connection for most internal circuits.
V
powers the entire chip except for the gate drivers. Externally
filtering this pin with a lowpass RC network (e.g.,
6
TYPICAL PERFOR A CE CHARACTERISTICS
TH1
IN
IN
U
/I
selects 750kHz operation; floating this pin selects
(Pin 5/Pin 8): Chip Signal Power Supply. This pin
TH2
(Pins 1, 8/Pins 4, 11): Current Threshold and
U
IN
20
18
16
14
12
10
to filter and smooth the changes in fre-
8
6
4
2
0
U
Shutdown Quiescent Current
vs Input Voltage
2
RUN/SS = 0V
3
(UF/GN Package)
W
4
INPUT VOLTAGE (V)
5
U
6
7
8
9
37361 G17
10
IN
),
R = 10Ω, C = 1µF) is suggested to minimize noise pickup,
especially in high load current applications.
TRACK (Pin 6/Pin 9): Tracking Input for Second Control-
ler. Allows the start-up of V
according to a ratio established by a resistor divider on
V
ing of V
with a ratio equal to those connected to V
should be used to connect to TRACK from V
PGOOD(Pin 9/Pin 12): Power Good Output Voltage Moni-
tor Open-Drain Logic Output. This pin is pulled to ground
when the voltage on either feedback pin (V
within ±13.3% of its nominal set point.
PGND (Pins 12, 16, 20, 25/Pins 15, 19, 23): Power Ground.
These pins serve as the ground connection for the gate
drivers and the negative input to the reverse current com-
parators. The Exposed Pad (UF package) must be soldered
to PCB ground.
RUN/SS (Pin 14/Pin 17): Run Control Input and Optional
External Soft-Start Input. Forcing this pin below 0.65V shuts
down the chip (both channels). Driving this pin to V
releasing this pin enables the chip, using the chip’s inter-
nal soft-start. An external soft-start can be programmed by
connecting a capacitor between this pin and ground.
OUT1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
connected to the TRACK pin. For one-to-one track-
0
OUT1
2
RUN/SS Start-Up Current
vs Input Voltage
RUN/SS = 0V
T
A
3
and V
= 25°C unless otherwise noted.
4
INPUT VOLTAGE (V)
OUT2
5
6
during start-up, a resistor divider
7
OUT2
8
to “track” that of V
37361 G18
9
10
FB1
FB2
, V
OUT1
from V
FB2
.
) is not
OUT1
IN
OUT2
37361f
or