LTC1871EMS#PBF Linear Technology, LTC1871EMS#PBF Datasheet - Page 10

• Manufacturer Part Number: LTC1871EMS#PBF
• Description: IC CONTRLR CURRENT MODE 10-MSOP
• Manufacturer: Linear Technology
• Type: Step-Up (Boost), Flyback, Sepicr

Specifications of LTC1871EMS#PBF

• Internal Switch(s): No
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 1.23 ~ 72 V
• Current - Output: 50mA
• Frequency - Switching: 50kHz ~ 1MHz
• Voltage - Input: 2.5 ~ 36 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Input Voltage: 36V
• Output Current: 50mA
• Output Voltage: 12V
• Supply Voltage Range: 2.5V To 36V
• No. Of Pins: 10
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 1 - Unlimited
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

LTC1871
OPERATION
MOSFET R
Burst Mode comparator B1 will turn off the power MOSFET
and scale back the quiescent current of the IC to 250μA
(sleep mode). In this condition, the load current will be
supplied by the output capacitor until the I
above the 50mV hysteresis of the burst comparator. At
light loads, short bursts of switching (where the average
inductor current is 20% of its maximum value) followed
by long periods of sleep will be observed, thereby greatly
improving converter effi ciency. Oscilloscope waveforms
illustrating Burst Mode operation are shown in Figure 3.
Pulse-Skip Mode Operation
With the MODE/SYNC pin tied to a DC voltage above 2V,
Burst Mode operation is disabled. The internal, 0.525V
buffered I
pin to directly control the current comparator from no
load to full load. With no load, the I
0.30V, the power MOSFET is turned off and sleep mode
is invoked. Oscilloscope waveforms illustrating this mode
of operation are shown in Figure 4.
10
Figure 4. LTC1871 Low Output Current Operation with
Burst Mode Operation Disabled (MODE/SYNC = INTV
50mV/DIV
50mV/DIV
TH
Figure 3. LTC1871 Burst Mode Operation
(MODE/SYNC = 0V) at Low Output Current
5A/DIV
5A/DIV
DS(ON)
V
V
OUT
OUT
I
I
burst clamp is removed, allowing the I
L
L
V
V
I
V
V
I
OUT
OUT
IN
OUT
IN
OUT
. If the I
= 3.3V
= 3.3V
= 500mA
= 500mA
= 5V
= 5V
MODE/SYNC = 0V
(Burst Mode OPERATION)
MODE/SYNC = INTV
(PULSE-SKIP MODE)
TH
10μs/DIV
2μs/DIV
pin drops below 0.30V, the
TH
CC
pin is driven below
TH
1871 F04
1871 F03
voltage rises
CC
)
TH
When an external clock signal drives the MODE/SYNC
pin at a rate faster than the chip’s internal oscillator, the
oscillator will synchronize to it. In this synchronized mode,
Burst Mode operation is disabled. The constant frequency
associated with synchronized operation provides a more
controlled noise spectrum from the converter, at the ex-
pense of overall system effi ciency of light loads.
When the oscillator’s internal logic circuitry detects a
synchronizing signal on the MODE/SYNC pin, the in-
ternal oscillator ramp is terminated early and the slope
compensation is increased by approximately 30%. As
a result, in applications requiring synchronization, it is
recommended that the nominal operating frequency of
the IC be programmed to be about 75% of the external
clock frequency. Attempting to synchronize to too high an
external frequency (above 1.3f
slope compensation and possible subharmonic oscillation
(or jitter).
The external clock signal must exceed 2V for at least 25ns,
and should have a maximum duty cycle of 80%, as shown
in Figure 5. The MOSFET turn on will synchronize to the
rising edge of the external clock signal.
MODE/
SYNC
Figure 5. MODE/SYNC Clock Input and Switching
Waveforms for Synchronized Operation
GATE
I
L
t
MIN
= 25ns
D = 40%
0.8T
O
) can result in inadequate
T
T = 1/f
1871 F05
O
2V TO 7V
1871fe