LTC1624IS8 Linear Technology, LTC1624IS8 Datasheet - Page 20

• Manufacturer Part Number: LTC1624IS8
• Description: IC SW REG CONTROLLER N-CH 8-SOIC
• Manufacturer: Linear Technology
• Type: Step-Down (Buck), Step-Up (Boost), Inverting, Sepicr

Specifications of LTC1624IS8

• Internal Switch(s): No
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 1.19 ~ 30 V
• Current - Output: 2A
• Frequency - Switching: 200kHz
• Voltage - Input: 3.5 ~ 36 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

LTC1624
APPLICATIONS
Positive-to-negative converters have high ripple current in
both the input and output capacitors. For long capacitor
lifetime, the RMS value of this current must be less than
the high frequency ripple rating of the capacitor.
The following formula gives an approximate value for RMS
ripple current. This formula assumes continuous mode
and low current ripple. Small inductors will give somewhat
higher ripple current, especially in discontinuous mode.
For the exact formulas refer to Application Note 44, pages
28 to 30. The input and output capacitor ripple current
(occurring at V
ff = Fudge factor (1.2 to 2.0)
The output peak-to-peak ripple voltage is:
The input capacitor can also see a very high surge current
when a battery is suddenly connected, and solid tantalum
capacitors can fail under this condition. Be sure to specify
surge tested capacitors.
Positive-to-Negative Converter: Duty Cycle
Limitations
The minimum on-time of 450ns sets a limit on how high
of input-to-output ratio can be tolerated while not skipping
cycles. This only impacts designs when very low output
voltages ( V
voltage is:
Positive-to-Negative Converter: Shutdown
Considerations
Since the ground pin on the LTC1624 is referenced to
– V
into shutdown. Shutdown is enabled by pulling the
20
V
V
Capacitor
OUT
V
IN(MAX)
IN(MAX)
OUT(P-P)
, additional circuitry is needed to put the LTC1624
< 36V – V
< 10.1V
OUT
= R
I
RMS
IN(MIN)
ESR
< 2.5V) are needed. The maximum input
U
OUT
(I
OUT
) is:
D(MAX)
ff I
+ 5V
INFORMATION
OUT
U
For absolute maximum ratings
)
For DC > 9%
V
V
OUT
W
IN
U
I
pin. With the LTC1624 ground pin referenced to – V
the nonimal range on the I
shutdown) to (– V
Figure 15, M2, M3 and R3 provide a level shift from typical
TTL levels to the LTC1624 operating as positive-to-nega-
tive converter. MOSFET M3 supplies gate drive to M2
during shutdown, while M2 pulls the I
– V
Step-Down Converters: PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1624. These items are also illustrated graphically in
the layout diagram of Figure 9. Check the following in your
layout:
1. Are the signal and power grounds segregated? The
2. Does the V
3. Does the V
4. Does the (+) plate of C
5. Keep the switch node SW away from sensitive small-
TH
LTC1624 ground (Pin 4) must return to the (–) plate
of C
resistors? The resistive divider R1, R2 must be con-
nected between the (+) plate of C
The 100pF capacitor should be as close as possible to
the LTC1624.
same point as R
routed together with minimum PC trace spacing? The
filter capacitor between V
close as possible to the LTC1624.
as possible? This capacitor provides the AC current to
the MOSFET(s). Also, does C
possible to the V
This capacitor also supplies the energy required to
recharge the bootstrap capacitor. Adequate input
decoupling is critical for proper operation.
signal nodes. Ideally, M1, L1 and D1 should be con-
nected as closely as possible at the switch node.
OUT
/RUN pin below 0.8V relative to the LTC1624 ground
, shutting down the LTC1624.
OUT.
FB
IN
(Pin 3) connect directly to the feedback
lead connect to the input voltage at the
OUT
SENSE
IN
+ 2.4V)(at Max I
and ground pin of the LTC1624?
and are the SENSE
IN
connect to R
IN
TH
and SENSE
/RUN pin is – V
IN
OUT
connect as close as
TH/RUN
and signal ground.
OUT
SENSE
). Referring to
–
–
pin voltage to
and V
should be as
as closely
OUT
IN
leads
OUT
(in
,