LT1738EG Linear Technology, LT1738EG Datasheet - Page 13
![IC DC/DC CONTRLR LOW NOIS 20SSOP](/photos/6/69/66947/lt1683eg_pbf_sml.jpg)
LT1738EG
Manufacturer Part Number
LT1738EG
Description
IC DC/DC CONTRLR LOW NOIS 20SSOP
Manufacturer
Linear Technology
Type
Step-Up (Boost), Cuk, Flybackr
Datasheet
1.LT1738EGPBF.pdf
(20 pages)
Specifications of LT1738EG
Internal Switch(s)
No
Synchronous Rectifier
No
Number Of Outputs
1
Voltage - Output
5 ~ 100 V
Frequency - Switching
20kHz ~ 250kHz
Voltage - Input
2.55 ~ 20 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Current - Output
-
Power - Output
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LT1738EG#TRPBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
APPLICATIO S I FOR ATIO
Smaller value capacitors can be made in two ways. The
first is simply combining two capacitors in series. The
equivalent capacitance is then (C1 • C2)/(C1 + C2).
The second method makes use of a capacitor divider. Care
should be taken that the voltage rating of the capacitor
satisfies the full voltage swing thus essentially the same
rating as the MOSFET.
The equivalent slew capacitance for Figure 2 is
(C1 • C2)/(C1 + C2 + C3).
Positive Output Voltage Setting
Sensing of a positive output voltage is usually done using
a resistor divider from the output to the FB pin. The
positive input to the error amp is connected internally to a
1.25V bandgap reference. The FB pin will regulate to this
voltage.
Referring to Figure 3, R1 is determined by:
The FB bias current represents a small error and can
usually be ignored for values of R1||R2 up to 10k.
One word of caution, sometimes a feedback zero is added
to the control loop by placing a capacitor across R1. If the
feedback capacitively pulls the FB pin above the internal
regulator voltage (2.4V), output regulation may be dis-
rupted. A series resistance with the feedback pin can
eliminate this potential problem. There is an internal clamp
on FB that clamps at 0.7V above the regulation voltage that
should also help prevent this problem.
R
1
R
Table 2
INPUT VOLTAGE
< 25V
50V
100V
2
V
1 25
OUT
.
CAP
U
1
C2
Figure 2
U
MOSFET DRAIN
CAPACITOR VALUE
C1
C3
1738 F02
2.5pF
5pF
1pF
W
U
Dual Polarity Output Voltage Sensing
Certain applications may benefit from sensing both posi-
tive and negative output voltages. When doing this each
output voltage resistor divider is individually set as previ-
ously described. When both FB and NFB pins are used, the
LT1738 will act to prevent either output from going
beyond its set output voltage. The highest output (lightest
load) will dominate control of the regulator. This technique
would prevent either output from going unregulated high
at no load. However, this technique will also compromise
output load regulation.
Shutdown
If SHDN is pulled low, the regulator will turn off. As the
SHDN pin voltage is increased from ground the internal
bandgap regulator will be powered on. This will set a 1.39V
threshold for turn on of the internal regulator that runs
Negative Output Voltage Setting
Negative output voltage can be sensed using the NFB pin.
In this case regulation will occur when the NFB pin is at
–2.5V. The nominal input bias current for the NFB is –25 A
(I
divider.
Referring to Figure 4, R1 is chosen such that:
A suggested value for R2 is 2.5k. The NFB pin is normally
left open if the FB pin is being used.
NFB
R
1
), which needs to be accounted for in setting up the
R
2
2 5
.
V
OUT
NFB PIN
FB PIN
I
R
NFB
2 25
•
2 5
Figure 3
.
Figure 4
R2
A
R2
R1
R1
1738 F03
V
–V
1738 F04
OUT
OUT
LT1738
13
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