LTC1530IS8-1.9 Linear Technology, LTC1530IS8-1.9 Datasheet - Page 6
![IC SW REG CNTRLR SYNC 1.9V 8SOIC](/photos/6/62/66297/8-soic_05-08-1610_sml.jpg)
LTC1530IS8-1.9
Manufacturer Part Number
LTC1530IS8-1.9
Description
IC SW REG CNTRLR SYNC 1.9V 8SOIC
Manufacturer
Linear Technology
Type
Step-Down (Buck)r
Datasheet
1.LTC1530CS8PBF.pdf
(24 pages)
Specifications of LTC1530IS8-1.9
Internal Switch(s)
No
Synchronous Rectifier
Yes
Number Of Outputs
1
Voltage - Output
1.9V
Current - Output
20A
Frequency - Switching
300kHz
Voltage - Input
3.3V, 5V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Power - Output
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LTC1530IS8-1.9
Manufacturer:
LT
Quantity:
10 000
Part Number:
LTC1530IS8-1.9#PBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
Part Number:
LTC1530IS8-1.9#TRPBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
LTC1530
PI FU CTIO S
PV
must connect to a potential of at least V
V
connected to the switching node between Q1 and Q2 (see
Figure 1) or connect PV
properly or erratic operation will result. A low ESR 10 F
capacitor or larger bypass capacitor along with a 0.1 F
surface mount ceramic capacitor in parallel is recom-
mended from PV
ripple. Switching ripple should be 100mV at the PV
pin.
GND (Pin 2): Power and Logic Ground. GND is connected
to the internal gate drive circuitry and the feedback cir-
cuitry. To obtain good output voltage regulation, use
proper ground techniques between the LTC1530 GND and
bottom-side FET source and the negative terminal of the
output capacitor. See the Applications Information section
for more details on PCB layout techniques.
V
able LTC1530, use an external resistor divider to set the
required output voltage. Connect the tap point of the
resistor divider network to V
divider network to the output voltage. For fixed output
voltage versions of the LTC1530, the resistor divider is
internal and the top of the resistor divider network is
brought out to V
network for each fixed output voltage version sinks ap-
proximately 30 A. Connect V
either at the output capacitors or at the actual point of load.
V
the pin. Isolate high current switching traces from this pin
and its PCB trace.
COMP (Pin 4): External Compensation. The COMP pin is
connected to the error amplifier output and the input of the
PWM comparator. An RC + C network is typically used at
6
IN
SENSE
SENSE
CC
U
= 5V, generate PV
(Pin 1): Power Supply for G1, G2 and Logic. PV
/V
/V
OUT
OUT
U
(Pin 3): Feedback Voltage Pin. For the adjust-
is sensitive to switching noise injected into
CC
OUT
directly to GND to minimize switching
U
. In general, the resistor divider
CC
CC
using a simple charge pump
to a 12V supply. Bypass PV
OUT
SENSE
to the output voltage
and the top of the
IN
+ V
GS(ON)Q1
. If
CC
CC
CC
COMP to compensate the feedback loop for optimum
transient response. To shut down the LTC1530, pull this
pin below 0.1V with an open-collector or open-drain
transistor. Supply current is typically reduced to 45 A in
shutdown. An internal 4 A pullup ensures start-up.
I
by the voltage drop across an external resistor connected
between the drain of Q1 and I
pared with the voltage across the R
MOSFET. The LTC1530 contains a 200 A internal pull-
down at I
source has a positive temperature coefficient to provide
first order correction for the temperature coefficient of the
external N-channel MOSFET’s R
I
switching node between Q1’s source and Q2’s drain. If I
drops below I
limit. Under this condition, the internal soft-start capacitor
is discharged and COMP is pulled low slowly. Duty cycle
is reduced and output power is limited. The current limit
circuitry is only activated if PV
start-up considerations as PV
the MOSFET’s R
what is measured under normal operating conditions. The
current limit circuit is disabled by floating I
ing I
G2 (Pin 7): Gate Drive for the Low Side N-Channel MOSFET,
Q2. This output swings from PV
if G1 is high or if the output is disabled. To prevent
undershoot during a soft-start cycle, G2 is held low until
G1 first transitions high.
G1 (Pin 8): Gate Drive for the Topside N-Channel MOSFET,
Q1. This output swings from PV
if G2 is high or if the output is disabled.
MAX
FB
(Pin 6): Current Limit Sense Pin. Connect I
FB
(Pin 5): Current Limit Threshold. Current limit is set
to PV
MAX
CC
MAX
.
to set current limit. This 200 A current
DS(ON)
with G1 on, the LTC1530 enters current
can be significantly higher than
CC
MAX
CC
CC
CC
DS(ON)
is ramping up because
to GND. It is always low
to GND. It is always low
. This voltage is com-
DS(ON)
8V. This action eases
.
of the high side
MAX
and short-
FB
to the
1530fa
FB