LT1424CS8-5 Linear Technology, LT1424CS8-5 Datasheet - Page 10

• Manufacturer Part Number: LT1424CS8-5
• Description: IC SW REG ISOLATD FLYBCK 5V8SOIC
• Manufacturer: Linear Technology
• Type: Flybackr

Specifications of LT1424CS8-5

• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 5V
• Current - Output: 200mA
• Frequency - Switching: 285kHz
• Voltage - Input: 2.8 ~ 20 V
• Operating Temperature: 0°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

OPERATION
time. Certain parameters of flyback amp behavior will then
be directly affected by the variable enable period. These
include effective transconductance and V
LOAD COMPENSATION THEORY
The LT1424-5 uses the flyback pulse to obtain information
about the isolated output voltage. A potential error source
is caused by transformer secondary current flow through
the real life nonzero impedances of the output rectifier,
transformer secondary and output capacitor. This has
been represented previously by the expression (I
However, it is generally more useful to convert this expres-
sion to an effective output impedance. Because the sec-
ondary current only flows during the off portion of the duty
cycle, the effective output impedance equals the lumped
secondary impedance times the inverse of the OFF duty
cycle. That is,
Expressing this in terms of the ON duty cycle, remember-
ing DC OFF = 1 – DC,
In less critical applications, or if output load current
remains relatively constant, this output impedance error
may be judged acceptable and the external R
value adjusted to compensate for nominal expected error.
In more demanding applications, output impedance error
may be minimized by the use of the load compensation
function.
To implement the load compensation function, a voltage
is developed that is proportional to average output switch
current. This voltage is then impressed across the inter-
nal R
LT1424-5
10
R
R
ESR = Lumped secondary impedance
DC OFF = OFF duty cycle
R
DC = ON duty cycle
OUT
OUT
OUT
OCOMP
= ESR
= Effective supply output impedance
= ESR
resistor and the resulting current is then
1 – DC
DC OFF
U
1
1
where,
C
node slew rate.
SEC
FB
resistor
)(ESR).
subtracted from the R
creases, average switch current increases to maintain
rough output voltage regulation. This causes an increase
in R
through which feedback loop action causes a corre-
sponding increase in target output voltage.
Assuming a relatively fixed power supply efficiency, Eff
Average primary side current may be expressed in terms
of output current as follows:
combining the efficiency and voltage terms in a single
variable,
Switch current is converted to voltage by a sense resistor
and amplified by the current sense amplifier with associ-
ated gain G. This voltage is then impressed across the
internal R
subtracted from the R
V
Nominal output impedance cancellation is obtained by
equating this expression with R
For simplicity, the data sheet refers to V
given as:
OUT
Power Out = (Eff)(Power In)
(V
I
I
K1 =
IN
IN
OCOMP
V
V
V
I
OUT
I
target is:
OUT
OUT
OUT
SW
=
= K1(I
REF
)(I
(V
(V
= K1( I
resistor current subtracted from the R
OUT
OCOMP
= K1(R
= (R
V
V
IN
IN
OUT
OUT
OUT
)(Eff)
)(Eff)
) = (Eff)(V
SENSE
) where,
SENSE
OUT
resistor to form a current that is
I
OUT
)(G)
FB
)
FB
IN
(R
)(G)
node. So the effective change in
)(I
R
node. As output loading in-
R
SENSE
OCOMP
OCOMP
IN
R
R
)
FB
OCOMP
OUT
R
)(G)
FB
.
R
REF
FB
/ I
and,
SW
sn14245 14245fs
FB
. This is
node,