LTC1771IS8 Linear Technology, LTC1771IS8 Datasheet - Page 6

IC CTRLR DC/DC STEPDOWN HE 8SOIC

LTC1771IS8

Manufacturer Part Number
LTC1771IS8
Description
IC CTRLR DC/DC STEPDOWN HE 8SOIC
Manufacturer
Linear Technology
Type
Step-Down (Buck)r
Datasheet

Specifications of LTC1771IS8

Internal Switch(s)
No
Synchronous Rectifier
No
Number Of Outputs
1
Voltage - Output
1.23 ~ 18 V
Current - Output
5A
Voltage - Input
2.8 ~ 18 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Power - Output
-
Frequency - Switching
-

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OPERATIO
Main Control Loop
The LTC1771 uses a constant off-time, current mode
step-down architecture. During normal operation, the
P-channel MOSFET is turned on at the beginning of each
cycle and turned off when the current comparator C
triggers the 1-shot timer. The external MOSFET switch
stays off for the 3.5 s 1-shot duration and then turns back
on again to begin a new cycle. The peak inductor current
at which C triggers the 1-shot is controlled by the voltage
on Pin 3 (I
external resistive divider connected between V
ground allows EA to receive an output feedback voltage
V
decrease in V
turn causes the I
inductor current matches the new load current.
The main control loop is shut down by pulling Pin 1
(RUN/SS) low. Releasing RUN/SS allows an internal 1 A
current source to charge soft-start capacitor C
C
I
mum value. As C
released allowing normal operation to resume.
Burst Mode Operation
The LTC1771 provides outstanding low current efficiency
and ultralow no-load supply current by using Burst Mode
operation when the MODE pin is pulled above 2V. During
Burst Mode operation, short burst cycles of normal switch-
ing are followed by a longer idle period with the switch off
and the load current is supplied by the output capacitor.
During this idle period, only the minimum required cir-
cuitry—1.23V reference and error amp—are left on, and
the supply current is reduced to 9 A. At no load, the output
capacitor is still discharged very slowly by leakage current
in the Schottky diode and feedback resistor current result-
ing in very low frequency burst cycles that add a few more
microamps to the supply current.
LTC1771
6
TH
FB
SS
. When the load current increases, it causes a slight
voltage clamped at approximately 40% of its maxi-
reaches 1V, the main control loop is enabled with the
TH
), the output of the error amplifier EA. An
FB
relative to the 1.23V reference, which in
TH
SS
U
continues to charge, I
voltage to increase until the average
(Refer to Functional Block Diagram)
TH
is gradually
SS
OUT
. When
and
Burst Mode operation is provided by clamping the mini-
mum I
maximum load current. If the load falls below this level, i.e.
the I
B switches state signaling the LTC1771 to enter sleep
mode. During this time, EA is reduced to 10% of its normal
operating current and the external compensation capaci-
tor is disconnected and clamped to 1V so that the EA can
drive its output with the lower available current. As the load
discharges the output capacitor, the internal I
increases. When it exceeds 1V the burst comparator exits
sleep mode, reconnects the external compensation com-
ponents to the error amplifier output, and returns EA to full
power along with the other necessary circuitry. This
scheme (patent pending) allows the EA to be reduced to
such a low operating current during sleep mode without
adding unacceptable delay to wake up the LTC1771 due to
the compensation capacitor on I
normal operation.
Burst Mode operation can be disabled by pulling the
MODE pin to ground. In this mode of operation, the burst
comparator B is disabled and the I
all the way to 0V. The load can now be reduced to about 1%
of maximum load before the loop skips cycles to maintain
regulation. This mode provides a low noise output spec-
trum, useful for reducing both audio and RF interference,
at the expense of reduced efficiency at light loads.
Off-Time
The off-time duration is 3.5 s when the feedback voltage
is close to the reference voltage; however, as the feedback
voltage drops, the off-time lengthens and reaches a maxi-
mum value of about 70 s when V
that the inductor current has enough time to decay when
the reverse voltage across the inductor is low such as
during short circuit, thus protecting the MOSFET and
inductor.
TH
TH
voltage tries to fall below 1V, the burst comparator
voltage at 1V which represents about 25% of
TH
TH
FB
required for stability in
voltage allowed to go
is zero. This ensures
TH
voltage

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