LTC3447EDD Linear Technology, LTC3447EDD Datasheet - Page 2

• Manufacturer Part Number: LTC3447EDD
• Description: IC CONV DC/DC SYNC BUCK 10DFN
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LTC3447EDD

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.69 ~ 2.05 V
• Current - Output: 600mA
• Frequency - Switching: 1MHz
• Voltage - Input: 2.5 ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-DFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

ABSOLUTE AXI U RATI GS
ELECTRICAL CHARACTERISTICS
LTC3447
(Note 1)
V
RUN, V
SW Voltage ................................... –0.3V to (V
SCL, SDA Voltages ................................... – 0.3V to V
P-Channel Switch Source Current (DC) ...............800mA
N-Channel Switch Sink Current (DC) ...................800mA
Peak SW Sink and Source Current ...........................1.3A
Operating Temperature Range (Note 2) ...–40°C to 85°C
Junction Temperature (Note 3) ............................. 125°C
Storage Temperature Range ...................–65°C to 125°C
temperature range, otherwise specifi cations are at T
SYMBOL
RUN
PGOOD
R
V
V
V
ΔV
I
V
V
I
f
R
R
I
FB
I
SCL
SCL
SDA
SDA
2
PK
S
OSC
LSW
FB
OUT(MIN)
OUT(MAX)
OUT
LOADREG
IN
VOUT
PFET
NFET
IN
OUT
THR
HYST
THR
, V
HYST
CCD
OUT
Voltages ....................................... –0.3V to 6V
, FB Voltages .............................. – 0.3V to V
PARAMETER
Run Threshold
Reports Undervoltage
Feedback Resistance
Regulated Output Voltage
Regulated Output Voltage
Output Voltage Step Size (6-bits)
Output Voltage Line Regulation
Peak Inductor Current
Output Voltage Load Regulation
Input Voltage Range
Input DC Bias Current
Burst Mode Operation
Active Mode
Shutdown
Nominal Oscillator Frequency
R
R
SW Leakage
Optional Start-Up Feedback Voltage
Feedback Input Current
I
I
I
I
2
2
2
2
DS(ON)
DS(ON)
C Clock Logic Threshold
C Clock Logic Hysteresis
C Data Logic Threshold
C Data Logic Hysteresis
W
of P-Channel FET
of N-Channel FET
W W
U
A
IN
= 25°C. V
CONDITIONS
PGOOD = 0.4V
V
Duty Cycle < 35%, Wafer Level
(Note 4)
I
V
V
V
V
I
I
V
Regulated Feedback Voltage
(Note 5)
(Note 5)
(Note 5)
(Note 5)
LOAD
SW
SW
+ 0.3V)
IN
OUT
RUN
OUT
OUT
RUN
The
= 2.5V to 5.5V (Note 6)
= 100mA, Wafer Level
= –100mA, Wafer Level
= 90%, I
= 100%
= 0V
= 0V, V
= 0V, V
CCD
= 0A
IN
●
IN
denotes the specifi cations which apply over the full operating
= 3.6V unless otherwise specifi ed.
IN
SW
LOAD
= 5.5V
PACKAGE/ORDER I
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
= 0V or 5V, V
T
JMAX
PGOOD
= 0A
V
GND
10-LEAD (3mm x 3mm)PLASTIC DFN
OUT
V
= 125°C, θ
FB
IN
EXPOSED PAD IS GND (PIN 11)
MUST BE SOLDERED TO PCB
1
2
3
4
5
IN
JA
DD PACKAGE
= 5V
TOP VIEW
= 43°C/W, θ
11
JC
= 2.96°C/W
10
9
8
7
6
●
●
●
●
●
●
SDA
V
SCL
RUN
SW
CCD
0.669
1.989
20.3
0.75
MIN
0.3
2.5
0.7
3
U
FOR ATIO
V
V
0.69
2.05
21.6
0.32
0.22
±0.1
TYP
460
280
160
300
300
ORDER PART
CCD/2
CCD/2
0.2
0.2
0.5
0.1
0.6
2.5
LTC3447EDD
34
1
1
1
MARKING
NUMBER
DD PART
LBKB
W
0.711
2.112
MAX
22.9
1.25
400
1.5
1.2
5.5
1.3
60
±1
10
1
1
UNITS
U
MHz
3447f
%/V
%/V
kHz
mA
mV
mV
mV
kΩ
µA
µA
µA
µA
nA
%
Ω
Ω
V
V
V
A
V
V
V
V