LT3500IDD#PBF Linear Technology, LT3500IDD#PBF Datasheet - Page 19

• Manufacturer Part Number: LT3500IDD#PBF
• Description: IC REG STP-DWN 2A 12-DFN
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LT3500IDD#PBF

• Topology: Step-Down (Buck) (1), Linear (LDO) (1)
• Function: Any Function
• Number Of Outputs: 2
• Frequency - Switching: 500kHz ~ 2.4MHz
• Voltage/current - Output 1: 0.8 ~ 38.9 V, 2A
• Voltage/current - Output 2: Adjustable, 13mA
• W/led Driver: No
• W/supervisor: No
• W/sequencer: No
• Voltage - Supply: 3 V ~ 36 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 12-DFN
• Current - Output: 2A
• Voltage - Output: 0.8 ~ 38.9 V
• Voltage - Input: 3 ~ 36 V
• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

APPLICATIONS INFORMATION
current proportional to the voltage at the V
the output capacitor integrates this current, and that the
capacitor on the V
output current, resulting in two poles in the loop. In
most cases a zero is required and comes from either the
output capacitor ESR or from a resistor in series with C
This simple model works well as long as the value of the
inductor is not too high and the loop crossover frequency
is much lower than the switching frequency. A phase lead
capacitor (C
the transient response.
Synchronization
The R
to an external clock source. Driving the R
with a clock source triggers the synchronization detection
circuitry. Once synchronization is detected, the rising edge
of SW will be synchronized to the rising edge of the R
pin signal. An AGC loop will adjust slope compensation
to avoid subharmonic oscillation.
The synchronizing clock signal input to the LT3500 must
have a frequency between 250kHz and 2.5MHz, a duty
cycle between 20% and 80%, a low state below 0.5V and
a high state above 1.6V. Synchronization signals outside
of these parameters will cause erratic switching behavior.
The R
running frequency ((V
approximately equal to the synchronization frequency. If
the synchronization signal is halted, the synchronization
detection circuitry will timeout in typically 10μs at which
time the LT3500 reverts to the free-running frequency based
on the current through R
above 1.1V at any time, switching will be disabled.
T
T
/SYNC pin can be used to synchronize the LT3500
/SYNC resistor should be set such that the free
PL
) across the feedback divider may improve
C
pin (C
RT/SYNC
T
/SYNC. If the R
C
) integrates the error amplifi er
– V
SYNCLO
T
/SYNC pin is held
T
C
/SYNC resistor
)/R
pin. Note that
RT/SYNC
T
/SYNC
) is
C
.
If the synchronization signal is not present during regu-
lator start-up (for example, the synchronization circuitry
is powered from the regulator output) the R
must see an equivalent resistance to ground between 15k
and 200k until the synchronization circuitry is active for
proper start-up operation.
If the synchronization signal powers up in an undetermined
state (V
to the LT3500 as shown in Figure 7. The circuit as shown
will isolate the synchronization signal when the output
voltage is below 90% of the regulated output. The LT3500
will start-up with a switching frequency determined by the
resistor from the R
If the synchronization signal powers up in a low impedance
state (V
and the synchronizing clock. The equivalent resistance
seen from the R
frequency.
If the synchronization signal powers up in a high impedance
state (Hi-Z), connect a resistor from the R
ground. The equivalent resistance seen from the R
pin to ground will set the start-up frequency.
Figure 7. Synchronous Signal Powered from Regulator’s Output
OL
OL
, V
), connect a resistor between the R
OH
LT3500
R
, Hi-Z), connect the synchronization clock
T
T
/SYNC
/SYNC pin to ground will set the start-up
LDRV
PG
T
/SYNC pin to ground.
V
SYNCHRONIZATION
CC
CIRCUITRY
CLK
T
LT3500
/SYNC pin to
3500 F07
T
T
/SYNC pin
/SYNC pin
T
19
/SYNC
3500fc