LTC1147CS8-5#PBF Linear Technology, LTC1147CS8-5#PBF Datasheet - Page 9

IC SW REG STEP-DOWN 5V 8-SOIC

LTC1147CS8-5#PBF

Manufacturer Part Number
LTC1147CS8-5#PBF
Description
IC SW REG STEP-DOWN 5V 8-SOIC
Manufacturer
Linear Technology
Type
Step-Down (Buck)r
Datasheet

Specifications of LTC1147CS8-5#PBF

Internal Switch(s)
No
Synchronous Rectifier
No
Number Of Outputs
1
Voltage - Output
5V
Current - Output
50mA
Frequency - Switching
400kHz
Voltage - Input
3.5 ~ 14 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power - Output
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LTC1147CS8-5#PBFLTC1147CS8-5
Manufacturer:
LINEAR/凌特
Quantity:
20 000
APPLICATIO S I FOR ATIO
used. For V
< 4V) may be used. If V
a logic-level threshold MOSFET (V
strongly recommended. When a logic-level MOSFET is
used, the LTC1147 supply voltage must be less than the
absolute maximum V
The maximum output current I
requirement for the power MOSFET. When the LTC1147
series is operating in continuous mode, the simplifying
assumption can be made that either the MOSFET or
Schottky diode is always conducting the average load
current. The duty cycles for the MOSFET and diode are
given by:
From the duty cycle the required R
can be derived:
where P
temperature dependency of R
mined by efficiency and/or thermal requirements (see
Efficiency Considerations). (1 + ) is generally given for a
MOSFET in the form of a normalized R
ture curve, but = 0.007/ C can be used as an approxima-
tion for low voltage MOSFETs.
Output Diode Selection (D1)
The Schottky diode D1 shown in Figure 1 only conducts
during the off-time. It is important to adequately specify
the diode peak current and average power dissipation so
as not to exceed the diode ratings.
The most stressful condition for the output diode is under
short circuit (V
must safely handle I
Under normal load conditions the average current con-
ducted by the diode is:
P-Ch Duty Cycle =
Schottky Diode Duty Cycle =
P-Ch R
P
is the allowable power dissipation and
DS(ON)
IN
> 8V, a standard threshold MOSFET (V
OUT
=
= 0V). Under this condition the diode
U
(V
SC(PK)
GS
OUT
V
IN
V
OUT
ratings for the MOSFET.
IN
U
is expected to drop below 8V,
)(I
(V
at close to 100% duty cycle.
MAX
MAX
IN
DS(ON)
)(P
(V
2
determines the R
DS(ON)
)(1 +
P
W
IN
)
. P
GS(TH)
DS(ON)
– V
P
V
for the MOSFET
P
OUT
IN
will be deter-
)
vs tempera-
< 2.5V) is
+ V
U
D
P
DS(ON)
GS(TH)
)
is the
Remember to keep lead lengths short and observe proper
grounding (see Board Layout Checklist) to avoid ringing
and increased dissipation.
The forward voltage drop allowable in the diode is calcu-
lated from the maximum short-circuit current as:
where P
determined by efficiency and/or thermal requirements
(see Efficiency Considerations).
C
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle V
prevent large voltage transients, a low ESR input capaci-
tor sized for the maximum RMS current must be used. The
maximum RMS capacitor current is given by:
This formula has a maximum at V
I
monly used for design because even significant devia-
tions do not offer much relief. Note that capacitor
manufacturer’s ripple current ratings are often based on
only 2000 hours of life. This makes it advisable to further
derate the capacitor, or to choose a capacitor rated at a
higher temperature than required. Several capacitors
may also be paralleled to meet size or height require-
ments in the design. Always consult the manufacturer if
there is any question. An additional 0.1 F to 1 F ceramic
decoupling capacitor is also required on V
high frequency decoupling.
The selection of C
series resistance (ESR). The ESR of C
than twice the value of R
LTC1147:
RMS
IN
V
I
C
C
D1
and C
F
IN
OUT
= I
=
Required I
OUT
I
D
(V
SC(PK)
Required ESR < 2R
OUT
P
is the allowable power dissipation and will be
IN
/2. This simple worst-case condition is com-
D
– V
Selection
LTC1147-5/LTC1147L
V
OUT
IN
RMS
OUT
+ V
is driven by the required effective
SENSE
D
I
MAX
)
(I
SENSE
LOAD
for proper operation of the
[V
LTC1147-3.3
OUT
)
IN
(V
OUT
IN
= 2V
V
– V
IN
IN
must be less
OUT
OUT
OUT
(Pin 1) for
sn1147 1147fds
/V
, where
)]
IN
1/2
. To
9

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