EL5525IRE Intersil, EL5525IRE Datasheet - Page 6

• Manufacturer Part Number: EL5525IRE
• Description: IC VREF GEN 18CH TFTLCD 38HTSSOP
• Manufacturer: Intersil

Specifications of EL5525IRE

• Applications: Converter, TFT, LCD
• Voltage - Input: 4.5 ~ 16.5 V
• Number Of Outputs: 18
• Voltage - Output: 0.5 ~ 14.95 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 38-TSSOP Exposed Pad, 38-eTSSOP, 38-HTSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Analog Section
Transfer Function
The transfer function is: shown in Equaion 1:
where data is the decimal value of the 10-bit data binary
input code.
The output voltages from the EL5525 will be derived from
the reference voltages present at the V
pins. The impedance between those two pins is about 32kΩ.
Care should be taken that the system design holds these two
reference voltages within the limits of the power rails of the
EL5525. GND < V
Clock Oscillator
The EL5525 requires an internal clock or external clock to
refresh its outputs. The outputs are refreshed at the falling OSC
clock edges. The output refreshed switches open at the rising
edges of the OSC clock. The driving load shouldn’t be changed
at the rising edges of the OSC clock. Otherwise, it will generate
a voltage error at the outputs. This clock may be input or output
via the clock pin labeled EXT_OSC. The internal clock is
provided by an internal oscillator running at approximately
21kHz and can be output to the EXT_OSC pin. In a 2 chip
system, if the driving loads are stable, one chip may be
programmed to use the internal oscillator; then the OSC pin will
output the clock from the internal oscillator. The second chip
may have the OSC pin connected to this clock source.
V
OUT IDEAL )
Control
C1
0
0
0
0
0
0
(
A4
=
0
0
0
0
0
1
PARAMETER
V
REFL
REFH
Channel Address
A3
t
t
t
t
t
0
0
0
0
0
0
t
HE
HD
SD
r
SE
T
W
/t
+
f
≤ V
data
------------ -
1024
A2
0
0
0
0
1
0
S
and GND ≤ V
×
6
A1
(
0
0
0
1
1
0
V
REFH
A0
0
0
0
1
1
1
- V
REFL
REFL
REFL
D9
TABLE 3. SERIAL PROGRAMMING EXAMPLES
0
1
1
1
0
0
and V
TABLE 2. SERIAL TIMING PARAMETERS
RECOMMENDED OPERATING RANGE
)
≤ V
D8
0
1
0
0
0
0
REFH
REFH
D7
0
1
0
0
0
0
(EQ. 1)
.
D6
0
1
0
0
0
0
EL5525
0.05 * T
0.50 * T
≥200ns
≥10ns
≥10ns
≥10ns
≥10ns
D5
0
1
0
0
0
0
Data
For transient load application, the external clock Mode
should be used to ensure all functions are synchronized
together. The positive edge of the external clock to the OSC
pin should be timed to avoid the transient load effect. The
Application Drawing shows the LCD H rate signal used, here
the positive clock edge is timed to avoid the transient load of
the column driver circuits.
After power on, the chip will start with the internal oscillator
mode. At this time, the EXT_OSC pin will be in a high
impedance condition to prevent contention. By setting pin 10
to high, the chip is on external clock mode. Setting pin 10 to
low, the chip is on internal clock mode.
D4
0
1
0
0
1
1
D3
0
1
0
0
1
1
D2
0
1
0
0
1
1
D1
Clock Period
Clock Rise/Fall Time
ENA Hold Time
ENA Setup Time
Data Hold Time
Data Setup Time
Clock Pulse Width
0
1
0
0
1
1
D0
0
1
0
1
1
1
Channel A, Value = 0
Channel A, Value = 1023
Channel A, Value = 512
Channel C, Value = 513
Channel H, Value = 31
Channel R, Value = 31
DESCRIPTION
Condition
September 21, 2010
FN7393.2